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- UID
- 852722
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-- Transmit Shift Register:
Txshift:
PROCESS (Reset, Txclk)
BEGIN
IF Reset=''1'' THEN
Txreg <= (OTHERS=>''0'') ;
Txtag1 <= ''0'' ;
Txtag2 <= ''0'' ;
Txparity <= ''0'' ;
Tx <= ''0'' ;
ELSIF Txclk''Event AND Txclk = ''1'' THEN
IF (Txdone AND Txdatardy) = ''1'' THEN
-- Initialize Registers And Load Next Byte Of Data
Txreg <= Txhold; -- Load Tx Register From Txhold
Txtag2 <= ''1''; -- Tag Bits For Detecting
Txtag1 <= ''1''; -- When Shifting Is Done
Txparity <= ''1''; -- Parity Bit.Initializing To 1==Odd Parity
Tx <= ''0''; -- Start Bit
ELSE
-- Shift Data
Txreg <= Txreg(1 TO 7) & Txtag1;
Txtag1 <= Txtag2;
Txtag2 <= ''0'';
-- Form Parity As Each Bit Goes By
Txparity <= Txparity XOR Txreg(0);
-- Shift Out Data Or Parity Bit Or Stop/Idle Bit
IF Txdone = ''1'' THEN
Tx <= ''1''; -- Stop/Idle Bit
ELSIF Paritycycle = ''1'' THEN
Tx <= Txparity; -- Parity Bit
ELSE
Tx <= Txreg(0); --Shift Data Bit
END IF;
END IF ;
END IF;
END PROCESS;
-- Paritycycle = 1 On Next To Last Cycle (When Txtag2 Has Reached Txreg(1))
-- (Enables Putting The Parity Bit Out On Tx)
Paritycycle <= Txreg(1) AND NOT (Txtag2 OR Txtag1 OR
Txreg(7) OR Txreg(6) OR Txreg(5) OR
Txreg(4) OR Txreg(3) OR Txreg(2));
-- Txdone = 1 When Done Shifting (When Txtag2 Has Reached Tx)
Txdone <= NOT (Txtag2 OR Txtag1 OR
Txreg(7) OR Txreg(6) OR Txreg(5) OR Txreg(4) OR
Txreg(3) OR Txreg(2) OR Txreg(1) OR Txreg(0));
Rx_proc: -- Shift Data On Each Rxclk When Not Idling
PROCESS (Reset, Rxclk)
BEGIN
IF Reset=''1'' THEN
Rxreg <= (OTHERS=>''0'') ;
Rxparity <= ''0'' ;
Paritygen <= ''0'' ;
Rxstop <= ''0'' ;
ELSIF Rxclk''Event AND Rxclk = ''1'' THEN
IF Rxidle = ''1'' THEN
-- Load All Ones When Idling
Rxreg <= (OTHERS=>''1'');
Rxparity <= ''1'';
Paritygen <= ''1''; -- Odd Parity
Rxstop <= ''0'';
ELSE
-- Shift Data When Not Idling
-- Bug In Assigning To Slices
-- Rxreg (0 TO 6) <= Rxreg (1 TO 7);
-- Rxreg(7) <= Rxparity;
Rxreg <= Rxreg (1 TO 7) & Rxparity;
Rxparity <= Rxstop;
Paritygen <= Paritygen XOR Rxstop;-- Form Parity As Data Shifts By
Rxstop <= Rx;
END IF ;
END IF;
END PROCESS;
Async: -- Rxidle Requires Async Preset Since It Is Clocked By Rxclk And
-- Its Value Determines Whether Rxclk Gets Generated
PROCESS ( Reset, Rxclk )
BEGIN
IF Reset = ''1'' THEN
Rxidle <= ''0'';
ELSIF Rxclk''EVENT And Rxclk = ''1'' THEN
Rxidle <= NOT Rxidle AND NOT Rxreg(0);
END IF;
END PROCESS Async;
Txio: -- Load Txhold And Set Txdatardy On Falling Edge Of Write
-- Clear Txdatardy On Falling Edge Of Txdone
PROCESS (Reset, Clkx16)
VARIABLE Wr1,Wr2: Std_logic; -- Write Signal Delayed 1 And 2 Cycles
VARIABLE Txdone1: Std_logic; -- Txdone Signal Delayed One Cycle
BEGIN
IF Reset=''1'' THEN
Txdatardy <= ''0'' ;
Wr1 := ''0'' ;
Wr2 := ''0'' ;
Txdone1 := ''0'' ;
ELSIF Clkx16''Event AND Clkx16 = ''1'' THEN
IF Wr1 = ''0'' AND Wr2= ''1'' THEN
-- Falling Edge On Write Signal. New Data In Txhold Latches
Txdatardy <= ''1'';
ELSIF Txdone = ''0'' AND Txdone1 = ''1'' THEN
-- Falling Edge On Txdone Signal. Txhold Has Been Read.
Txdatardy <= ''0'';
END IF; |
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