-- Delayed Versions Of Write And Txdone Signals For Edge Detection
Wr2 := Wr1;
Wr1 := Write;
Txdone1 := Txdone;
END IF ;
END PROCESS;
Rxio:
PROCESS (Reset, Clkx16)
VARIABLE Rd1, Rd2 : Std_logic; -- Read Input Delayed 1 And 2 Cycles
VARIABLE Rxidle1 : Std_logic; -- Rxidle Signal Delayed 1 Cycle
BEGIN
IF Reset=''1'' THEN
Overrun <= ''0'' ;
Rxhold <= (OTHERS=>''0'') ;
Parityerr <= ''0'' ;
Framingerr <= ''0'' ;
Rxdatardy <= ''0'' ;
Rd1 := ''0'' ;
Rd2 := ''0'' ;
Rxidle1 := ''0'' ;
ELSIF Clkx16''Event AND Clkx16 = ''1'' THEN
-- Look For Rising Edge On Idle And Update Output Registers
IF Rxidle = ''1'' AND Rxidle1 = ''0'' THEN
IF Rxdatardy = ''1'' THEN
-- Overrun Error If Previous Data Is Still There
Overrun <= ''1'';
ELSE
-- No Overrun Error Since Holding Register Is Empty
Overrun <= ''0'';
-- Update Holding Register
Rxhold <= Rxreg;
-- Paritygen = 1 If Parity Error
Parityerr <= Paritygen;
-- Framingerror If Stop Bit Is Not 1
Framingerr <= NOT Rxstop;
-- Signal That Data Is Ready For Reading
Rxdatardy <= ''1'';
END IF;
END IF;
Rxidle1 := Rxidle; -- Rxidle Delayed 1 Cycle For Edge Detect
-- Clear Error And Data Registers When Data Is Read
IF (NOT Rd2 AND Rd1) = ''1'' THEN
Rxdatardy <= ''0'';
Parityerr <= ''0'';
Framingerr <= ''0'';
Overrun <= ''0'';
END IF;
Rd2 := Rd1; -- Edge Detect For Read
Rd1 := Read; -- (Must Be Assigned AFTER Reference)
IF Reset = ''1'' THEN
Rxdatardy <= ''0'';
END IF;
END IF ;
END PROCESS;
-- Drive Data Bus Only During Read
Data <= Rxhold WHEN Read = ''1'' ELSE (OTHERS=>''Z'') ;
-- Latch Data Bus During Write
Txhold <= Data WHEN Write = ''1'' ELSE Txhold;
-- Receive Data Ready Output Signal
Rxrdy <= Rxdatardy;
-- Transmitter Ready For Write When No Data Is In Txhold
Txrdy <= NOT Txdatardy;
-- Run-Time Simulation Check For Transmit Overrun
ASSERT Write = ''0'' OR Txdatardy = ''0''
REPORT "Transmitter Overrun Error" SEVERITY WARNING;
END Exemplar; |
