ADC3_IRQHandler ;148
DCD FSMC_IRQHandler ;149
DCD SDIO_IRQHandler ;150
DCD TIM5_IRQHandler ;151
DCD SPI3_IRQHandler ;152
DCD
UART4_IRQHandler ;153
DCD UART5_IRQHandler ;154
DCD TIM6_IRQHandler
;155
DCD TIM7_IRQHandler ;156
DCD DMA2_Channel1_IRQHandler 157
DCD DMA2_Channel2_IRQHandler ;158
DCD DMA2_Channel3_IRQHandler ;159
DCD DMA2_Channel4_5_IRQHandler ;160
AREA |.text|, CODE, READONLY ;161
Reset_Handler PROC ;162
EXPORT Reset_Handler ;163
IF
DATA_IN_ExtSRAM == 1 ;164
LDR R0,= 0x00000114 ;165
LDR R1,= 0x40021014 ;166
STR R0,[R1] ;167
LDR R0,= 0x000001E0 ;168
LDR R1,=
0x40021018 ;169
STR R0,[R1] ;170
LDR R0,= 0x44BB44BB ;171
[page]
LDR R1,= 0x40011400 ;172
STR R0,[R1] ;173
LDR
R0,= 0xBBBBBBBB ;174
LDR R1,= 0x40011404 ;175
STR R0,[R1] ;176
LDR R0,= 0xB44444BB ;177
LDR R1,= 0x40011800 ;178
STR
R0,[R1] ;179
LDR R0,= 0xBBBBBBBB ;180
LDR R1,= 0x40011804 ;181
STR R0,[R1] ;182
LDR R0,= 0x44BBBBBB ;183
LDR R1,=
0x40011C00 ;184
STR R0,[R1] ;185
LDR R0,= 0xBBBB4444 ;186
LDR
R1,= 0x40011C04 ;187
STR R0,[R1] ;188
LDR R0,= 0x44BBBBBB ;189
LDR R1,= 0x40012000 ;190
STR R0,[R1] ;191
LDR R0,=
0x44444B44 ;192
LDR R1,= 0x40012004 ;193
STR R0,[R1] ;194
LDR
R0,= 0x00001011 ;195
LDR R1,= 0xA0000010 ;196
STR R0,[R1] ;197
LDR R0,= 0x00000200 ;198
LDR R1,= 0xA0000014 ;199
STR
R0,[R1] ;200
ENDIF ;201
IMPORT __main ;202
LDR R0, =__main ;203
BX R0 ;204
ENDP ;205
ALIGN ;206
IF  EF:__MICROLIB ;207
EXPORT __initial_sp ;208
EXPORT __heap_base ;209
EXPORT
__heap_limit ;210
ELSE ;211
IMPORT __use_two_region_memory ;212
EXPORT __user_initial_stackheap ;213
__user_initial_stackheap ;214
LDR R0, = Heap_Mem ;215
LDR R1, = (Stack_Mem + Stack_Size) ;216
LDR R2, = (Heap_Mem + Heap_Size) ;217
LDR R3, = Stack_Mem ;218
BX LR ;219
ALIGN ;220
ENDIF ;221
END ;222
ENDIF ;223
END ;224 |
