ERROR:Pack:2310 - Too many comps of type "SLICEL" found ..怎么解决 芯片, system, ERROR

mp699

关于system generator生成bitstream中ERRORack:2310 - Too many .. SLICEL..刚使用这个，在关于system generator生成bitstream时，遇到错误，想请问下各位大侠这个错误怎么解决？非常感谢
当前使用xilinx ISE12.4
MATLAB2010B
芯片为spartan 3a xc3s200
错误提示如下：
WARNING:.........
.........................
ERRORack:2310 - Too many comps of type "SLICEL" found to fit this device.

ERRORack:18 - The design is too large for the given device and package.

   Please check the Design Summary section to see which resource requirement for

   your design exceeds the resources available in the device.


   NOTE: An NCD file will still be generated to allow you to examine the mapped

   design.  This file is intended for evaluation use only, and will not process

   successfully through PAR.


   This mapped NCD file can be used to evaluate how the design's logic has been

   mapped into FPGA logic resources.  It can also be used to analyze

   preliminary, logic-level (pre-route) timing with one of the Xilinx static

   timing analysis tools (TRCE or Timing Analyzer).


Design Summary:

Number of errors:      2

Number of warnings:  108

Logic Utilization:

  Number of Slice Flip Flops:         1,676 out of   3,584   46%

  Number of 4 input LUTs:             3,031 out of   3,584   84%

Logic Distribution:

  Number of occupied Slices:          1,990 out of   1,792  111% (OVERMAPPED)

    Number of Slices containing only related logic:   1,990 out of   1,990 100%

    Number of Slices containing unrelated logic:          0 out of   1,990   0%

      *See NOTES below for an explanation of the effects of unrelated logic.

  Total Number of 4 input LUTs:       3,511 out of   3,584   97%

    Number used as logic:             2,809

    Number used as a route-thru:        480

    Number used for Dual Port RAMs:     136

      (Two LUTs used per Dual Port RAM)

    Number used as Shift registers:      86


  The Slice Logic Distribution report is not meaningful if the design is

  over-mapped for a non-slice resource or if Placement fails.


  Number of bonded IOBs:                154 out of     195   78%

  Number of BUFGMUXs:                     1 out of      24    4%

  Number of MULT18X18SIOs:               15 out of      16   93%

  Number of RAMB16BWEs:                  13 out of      16   81%


Average Fanout of Non-Clock Nets:                2.44


Peak Memory Usage:  203 MB

Total REAL time to MAP completion:  8 secs

Total CPU time to MAP completion:   8 secs


NOTES:


   Related logic is defined as being logic that shares connectivity - e.g. two

   LUTs are "related" if they share common inputs.  When assembling slices,

   Map gives priority to combine logic that is related.  Doing so results in

   the best timing performance.


   Unrelated logic shares no connectivity.  Map will only begin packing

   unrelated logic into a slice once 99% of the slices are occupied through

   related logic packing.


   Note that once logic distribution reaches the 99% level through related

   logic packing, this does not mean the device is completely utilized.

   Unrelated logic packing will then begin, continuing until all usable LUTs

   and FFs are occupied.  Depending on your timing budget, increased levels of

   unrelated logic packing may adversely affect the overall timing performance

   of your design.


Mapping completed.

See MAP report file "controlboard_cw_map.mrp" for details.

Problem encountered during the packing phase.

ERROR:Xflow - Program map returned error code 2. Aborting flow execution...