各位用过ise得大虾请进 ise, 大虾

lianzishu

我是初学者，在学习中遇到下列问题：

请各位指点：

entity bit_rtl_adder is
   port (
   in1  :IN bit_vector;
   in2  :IN bit_vector;
   cntl : bit;
   pout : out bit_vector
   );
end bit_rtl_adder;
 
architecture func of bit_rtl_adder is
begin
p1: process(cntl)
   begin
   if cntl='1' then
   pout <= in1+in2;
      end if;
   end process;
end  func;

--
--# ** Error: bit_rtl_adder.vhd(17): No feasible entries for infix operator "+".
--# ** Error: bit_rtl_adder.vhd(17): Type error resolving infix expression "+".
--# ** Error: bit_rtl_adder.vhd(19): VHDL Compiler exiting
--# ** Error: C:/Modeltech_6.0d/win32/vcom failed.
--# Executing ONERROR command at macro ./test.ado line 10
--ERROR: VSim failed to simulate annotated testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity 3_8 is
    port(a,b,c,g1,g2a,g2b:in std_logic;
       yut std_logic_vector(7 downto 0));
end 3_8;

architecture 3_8_1 of 3_8 is
  signal indata:std_logic_vector(2 downto 0);
begin
  indata<=c&b&a;
  process(indata,g,g2a,g2b)
  begin
      if(g1='1'and g2a='0'and g2b='0')then
        case indata is
        when "000"=>y<="11111110";
      when "001"=>y<="11111101";
      when "010"=>y<="11111011";
      when "011"=>y<="11110111";
      when "100"=>y<="11101111";
      when "101"=>y<="11011111";
      when "110"=>y<="10111111";
      when "111"=>y<="01111111";
             end case;
         else
           y<="11111111";
         end if;
     end process;
end 3_8_1;

--# ** Warning: (vlib-34) Library already exists at "work".
--# resume
--# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
--# -- Loading package standard
--# -- Loading package std_logic_1164
--# -- Loading package std_logic_arith
--# -- Loading package std_logic_unsigned
--# -- Compiling entity s38
--# -- Compiling architecture behavioral of s38
--# ** Error: s38.vhd(52): String literal has a character 'x' not in the enumeration --type std_logic.
--# ** Error: s38.vhd(52): Expected length is 8; string length is 0.
--# ** Error: s38.vhd(58): VHDL Compiler exiting
--# ** Error: C:/Modeltech_6.0d/win32/vcom failed.
--# Executing ONERROR command at macro ./test38.ado line 10
--ERROR: VSim failed to simulate annotated testbench

 

这些错误是怎么回事