设计的是一个状态机，编译的时候出问题了，就是下面蓝色type语句出问题： 上面红色的代码已经有了s1,s2...s7声明，所以错误是：Error (10465): VHDL error at enum_encoding.vhd(17): name "s1" cannot be used because it is already used for a previously declared item 用s1,s2...s7表示常数应该可以吧，为什么有错误呢？请指教。（若没有红色部分代码，则没有错误） library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity enum_encoding is
port(clock,reset: in std_logic;
a,b,c,d,e: in boolean;
sub,multi,add: out std_logic);
end enum_encoding;
architecture archi of enum_encoding is
constant s1: std_logic_vector:="001";
constant s2: std_logic_vector:="010";
constant s3: std_logic_vector:="011";
constant s4: std_logic_vector:="100";
constant s5: std_logic_vector:="101";
constant s6: std_logic_vector:="110";
constant s7: std_logic_vector:="111";
type state_type is(s1,s2,s3,s4,s5,s6,s7);
signal cs,ns:state_type;
begin
process(clock,reset)
begin
if(reset='1') then
cs<=s1;
elsif (clock'event and clock='1')then
cs<=ns;
end if;
end process;
process(cs,a,b,c,d,e)
begin
case cs is
when s1=>
multi<='0';
add<='0';
sub<='0';
if(a and not b and c) then
ns<=s2;
elsif(a and b and not c) then
ns<=s4;
else
ns<=s1;
end if;
when s2=>
multi<='1';
add<='0';
sub<='0';
if(not d ) then
ns<=s3;
else
ns<=s4;
end if;
when s3=>
multi<='0';
add<='1';
sub<='0';
if(a or d) then
ns<=s4;
else
ns<=s3;
end if;
when s4=>
multi<='1';
add<='1';
sub<='0';
if(a and b and not c) then
ns<=s5;
else
ns<=s4;
end if;
when s5=>
multi<='1';
add<='0';
sub<='0';
ns<=s6;
when s6=>
multi<='0';
add<='1';
sub<='1';
if(not e) then
ns<=s7;
else
ns<=s6;
end if;
when s7=>
multi<='0';
add<='1';
sub<='0';
if(e) then
ns<=s1;
else
ns<=s7;
end if;
end case;
end process;
end archi;
| 
