各位大侠,小弟刚开始学vhdl，这是我下载的模数转换器vhdl程序，但是不知道在Quartus ii中如何验证它的波形是否正确？不知道怎么设置模拟输入量？最好有详细步骤，感激不尽～～～
--ADC0809.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adc0809 is
port(
data_in : in std_logic_vector(7 downto 0);--0809的8位转换数据输入
rst : in std_logic;--复位信号
clk : in std_logic;--转换工作时钟信号
eoc : in std_logic;--0809的转换结束控制信号
ale : out std_logic;--0809的通道选择地址锁存信号
start: out std_logic;--0809的转换启动控制信号
oe : out std_logic;--0809的输出使能控制信号
addr: out std_logic;--0809的通道选择控制信号
bcdout: out std_logic_vector(11 downto 0)
--来自0809的数据经bcd转换后的输出
);
end entity adc0809; architecture behav of adc0809 is
type states is(st0,st1,st2,st3,st4,st5,st6);
signal current_state,next_state: states;
signal regl: std_logic_vector(7 downto 0);
signal lock0,lock1: std_logic;--转换后数据输出锁存时钟信号
signal value :std_logic_vector(11 downto 0);
signal cen :std_logic;
signal ale0 : std_logic;
signal start0 : std_logic;
signal oe0 : std_logic;
begin
--A/D转换控制模块
statesystem: block is
begin
addr<='1';--状态转换控制
pro:process(current_state,eoc)
begin
case current_state is
when st0=>ale0<='0';start0<='0';oe0<='0';lock0<='0';
next_state<=st1;cen<='0';
when st1=>ale0<='1';start0<='0';oe0<='0';lock0<='0';
next_state<=st2;cen<='0';
when st2=>ale0<='0';start0<='1';oe0<='0';lock0<='0';
next_state<=st3;cen<='0';
when st3=>ale0<='0';start0<='0';oe0<='0';lock0<='0';
cen<='0';
if eoc='1' then--测试eoc的下降沿
next_state<=st3;
else
next_state<=st4;
end if;
when st4=>ale0<='0';start0<='0';oe0<='0';lock0<='0';
cen<='0';
if eoc='0' then--测试eoc的上升沿，=1表明转换结束
next_state<=st4;
else
next_state<=st5;
end if;
when st5=>ale0<='0';start0<='0';oe0<='1';lock0<='0';
next_state<=st5;cen<='1';
when st6=>ale0<='0';start0<='0';oe0<='1';lock0<='1';
next_state<=st0;cen<='0';
when others=>ale0<='0';start0<='0';oe0<='0';lock0<='0';
next_state<=st0;cen<='0';
end case;
end process pro; process(rst,clk)
begin
if rst='1' then
current_state<=st0;
elsif rising_edge(clk) then
current_state<=next_state;--在时钟的上升沿，转换至下一状态
end if;
end process;
--用于给输出信号去毛刺
process(clk) is
begin
if rising_edge(clk) then
ale<=ale0;start<=start0;oe<=oe0;lock1<=lock0;
end if;
end process;
--数据锁存进程
process(lock1)
begin
if rising_edge(lock1) then
regl<=data_in;--在lock1的上升沿，将转换好的数据锁入
end if;
end process;
end block statesystem; --A/D转换数据的bcd码转换模块
conversion: block is
signal v : std_logic_vector(7 downto 0);
signal hb,lb : std_logic_vector(11 downto 0);
signal c30,c74,c118: std_logic;
signal tempa,tempb,tempc: std_logic_vector(4 downto 0);
begin
process(regl) is
begin
v<=regl;
--将A/D转换后的数据的高4位通过查表的方式用12位bcd码表示
case v(7 downto 4) is
when "1111"=>hb<="010010000000";--4.80
when "1110"=>hb<="010001001000";--4.48
when "1101"=>hb<="010000010110";--4.16
when "1100"=>hb<="001110000100";--3.84
when "1011"=>hb<="001101010010";--3.52
when "1010"=>hb<="001100100000";--3.20
when "1001"=>hb<="001010001000";--2.88
when "1000"=>hb<="001001010110";--2.56
when "0111"=>hb<="001000100100";--2.24
when "0110"=>hb<="000110010010";--1.92
when "0101"=>hb<="000101100000";--1.60
when "0100"=>hb<="000100101000";--1.28
when "0011"=>hb<="000010010110";--0.96
when "0010"=>hb<="000001100100";--0.64
when "0001"=>hb<="000000110010";--0.32
when others=>hb<="000000000000";--0.00
end case;
--将A/D转换后数据的低4位用12位的bcd码表示
case v(3 downto 0) is
when "1111"=>lb<="000000110000";--0.30
when "1110"=>lb<="000000101000";--0.28
when "1101"=>lb<="000000100110";--0.26
when "1100"=>lb<="000000100100";--0.24
when "1011"=>lb<="000000100010";--0.22
when "1010"=>lb<="000000100000";--0.20
when "1001"=>lb<="000000011000";--0.18
when "1000"=>lb<="000000010110";--0.16
when "0111"=>lb<="000000010100";--0.14
when "0110"=>lb<="000000010010";--0.12
when "0101"=>lb<="000000010000";--0.10
when "0100"=>lb<="000000001000";--0.08
when "0011"=>lb<="000000000110";--0.06
when "0010"=>lb<="000000000100";--0.04
when "0001"=>lb<="000000000010";--0.02
when others=>lb<="000000000000";--0.00
end case;
end process;
--将A/D转换后数据的高、低4位的12位bcd码进行加法操作处理
process(hb,lb,cen) is
variable temp1,temp2,temp3: std_logic_vector(3 downto 0);
begin
if rising_edge(cen) then
temp1:=hb(3 downto 0)+lb(3 downto 0);
if temp1>"1001" then
temp1:=temp1+"0110";
temp2:=hb(7 downto 4)+lb(7 downto 4)+'1';
if temp2>"1001" then
temp2:=temp2+"0110";
temp3:=hb(11 downto 8)+lb(11 downto 8)+'1';
if temp3>"1001" then
temp3:=temp3+"0110";
end if;
else
temp3:=hb(11 downto 8)+lb(11 downto 8);
if temp3>"1001" then
temp3:=temp3+"0110";
end if;
end if;
else
temp2:=hb(7 downto 4)+lb(7 downto 4);
if temp2>"1001" then
temp2:=temp2+"0110";
temp3:=hb(11 downto 8)+lb(11 downto 8)+'1';
if temp3>"1001" then
temp3:=temp3+"0110";
end if;
else
temp3:=hb(11 downto 8)+lb(11 downto 8);
if temp3>"1001" then
temp3:=temp3+"0110";
end if;
end if;
end if;
end if;
value<=temp3&temp2&temp1;
end process;
--将经过bcd码转换处理后的数据输出
bcdout<=value;
end block conversion;
end architecture behav; [em06][em06] | 
