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- UID
- 138652
- 性别
- 男
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这几天我遇到一个问题，请您帮忙分析一下：我写的定时器中定义了一个信号：
signal count : STD_LOGIC_VECTOR(15 downto 0);
在综合时发生错误：
Analyzing Entity <component_38> (Architecture <behavioral>).
Entity <component_38> analyzed. Unit <component_38> generated.
Analyzing Entity <scq> (Architecture <behavioral>).
Entity <scq> analyzed. Unit <scq> generated.
Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.
Analyzing Entity <fpq> (Architecture <behavioral>).
Entity <fpq> analyzed. Unit <fpq> generated.
Analyzing Entity <dsq> (Architecture <behavioral>).
ERROR:Xst:827 - "E:/dj_vhdl/dsq/dsq.vhd" line 42: Signal count cannot be synthesized, bad synchronous description.
-->
Total memory usage is 89604 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
我仔细检查了一下，也没看出什么不对。下面是dsq代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dsq is
Port ( clk : in STD_LOGIC;
ce : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (15 downto 0);
stop : out STD_LOGIC);
end dsq;
architecture Behavioral of dsq is
signal count : STD_LOGIC_VECTOR(15 downto 0);
begin
process(clk,ce)
begin
if (ce'event and ce = '1') then
count <= datain;
end if;
if(ce = '1') then
if(clk'event and clk = '1') then
if(count /= "0000000000000000") then
count <= count - '1';
end if;
end if;
else count <= "0000000000000000";
end if;
end process;
stop <= '1' when count = "0000000000000000" else '0';
end Behavioral;
请帮我看看，谢谢！ |
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