我要在DE2板上实现静态图像显示，用的是DMA方式。我自己定义了一个VGA流模式控制器，在顶层模块图上直接调用没有问题，行场同步信号输出都正确，但是作为定制外设放入处理器内部就没有行场同步信号输出了，但vgaclk输出正常，那位高手帮我看看问题出在什么地方，谢谢！
VGA控制器源代码如下：
module vga_controller_stream(
address, iclk, reset,chipselect,write，writedata,readyfordata, endofpacket, hsync,
vsync,
sync,
blank,
vgaclk,
oVGA_R,
oVGA_G,
oVGA_B
);
input address;
input iclk;
input reset;
input chipselect;
input write;
input [31:0]writedata;
output readyfordata;
output endofpacket;
output hsync;
output vsync;
output sync;
output blank;
output vgaclk;
output [9:0] oVGA_R;
output [9:0] oVGA_G;
output [9:0] oVGA_B;
wire readyfordata;
wire endofpacket;
wire hsync;
wire vsync;
wire sync;
wire blank;
wire [31:0]pix_val;
wire read_next_pixel;
wire end_of_picture;
wire [9:0] fifo_cnt;
reg [19:0] pixel_count;
reg sync_end_of_picture;
wire vgaclk;
assign readyfordata=((fifo_cnt<10'd1000)&&(pixel_count<(640*480))&&(!sync_end_of_picture))?1'b1:1'b0;
always @(posedge iclk or posedge reset)
begin
if(reset==1'b1)
begin
pixel_count<=11'h000;
sync_end_of_picture<=1'b0;
end
else
begin
sync_end_of_picture<=end_of_picture;
if(sync_end_of_picture&&(pixel_count>((640*480)-1)))
begin
pixel_count<=20'h000;
end
else
begin
if(chipselect&&write&&readyfordata)
begin
pixel_count<=pixel_count+1'b1;
end
end
end
end
vga_timing vga_timing_inst(
.iRST_N(reset),
.oVGA_CLOCK(vgaclk),
.oVGA_H_SYNC(hsync),
.oVGA_V_SYNC(vsync),
.pix_val(pix_val),
.oVGA_BLANK(blank),
.read_next_pixel(read_next_pixel),
.end_of_picture(end_of_picture),
.oVGA_R(oVGA_R),
.oVGA_G(oVGA_G),
.oVGA_B(oVGA_B),
.iCLK(iclk)
);
fifo fifo_inst(
.aclr(sync_end_of_picture),
.clock(iclk),
.data(writedata),
.rdreq(read_next_pixel),
.wrreq(chipselect&write&readyfordata),
.q(pix_val),
.usedw(fifo_cnt)
);
endmodule | 
