20M信号都是ns级的,延时也只延时几ns,一般的硬件固有的延时也有几ns吧?这样是不是太不精确? 我写了个计数的,你看看 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity move72 is port(clk20:in std_logic_vector(4 downto 0); clk:in std_logic; control:in std_logic_vector(2 downto 0); sut std_logic); end; architecture move of move72 is signal q1:integer ; signal q2:integer ; signal q3:integer ; signal q4:integer ; signal y:std_logic_vector(4 downto 0); begin y(0)<=clk20(0);
process(clk) begin
if(clk'event and clk='1')then q1<=q1 +1; end if; if q1>=1 then y(1)<=clk20(1); else y(1)<='0'; end if; end process; process(clk) begin
if(clk'event and clk='1')then q2<=q2 +1; end if; if q2>=2 then y(2)<=clk20(2); else y(2)<='0'; end if; end process; process(clk) begin
if(clk'event and clk='1')then q3<=q3 +1; end if; if q3>=3 then y(3)<=clk20(3); else y(3)<='0'; end if; end process; process(clk) begin
if(clk'event and clk='1')then q4<=q4 +1; end if; if q4>=4 then y(4)<=clk20(4); else y(4)<='0'; end if; end process; process(control) begin case control is when "000"=>s<=y(0); when "001"=>s<=y(1); when "010"=>s<=y(2); when "011"=>s<=y(3); when "100"=>s<=y(4); when others=>s<='0'; end case; end process; end;