FPGA verilog 实现的1602 时钟计数器 (转)(2)
- UID
- 1029342
- 性别
- 男
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FPGA verilog 实现的1602 时钟计数器 (转)(2)
always @(posedge clk or negedge rst ) //时钟计数器
begin
if(!rst)
begin
shi<=0;fen<=0;miao<=0;
count1<=0;
end
else
begin
en_sel<=1;
two_7<= (shi/10)+8'b00110000;
two_8<= (shi%10)+8'b00110000;
two_10<=(fen/10)+8'b00110000;
two_11<=(fen%10)+8'b00110000;
two_13<=(miao/10)+8'b00110000;
two_14<=(miao%10)+8'b00110000;
count1<=count1+1'b1;
if(count1==49999999) // 时钟计数
begin
count1<=0;
miao<=miao+1;
if(miao==59)
begin
miao<=0;
fen<=fen+1;
if(fen==59)
begin
fen<=0;
shi<=shi+1;
if(shi==23)
begin
shi<=0;
end
end
end
end
end
end
always @(posedge lcd_clk )
begin
case(next)
state0 :
begin rs<=0; data<=8'h38; next<=state1; end //配置液晶
state1 :
begin rs<=0; data<=8'h0e; next<=state2; end
state2 :
begin rs<=0; data<=8'h06; next<=state3; end
state3 :
begin rs<=0; data<=8'h01; next<=state4; end
state4 :
begin rs<=0; data<=8'h80; next<=data0; end //显示第一行
data0 :
begin rs<=1; data<=one_1; next<=data1 ; end
data1 :
begin rs<=1; data<=one_2; next<=data2 ; end
data2 :
begin rs<=1; data<=one_3; next<=data3 ; end
data3 :
begin rs<=1; data<=one_4; next<=data4 ; end
data4 :
begin rs<=1; data<=one_5; next<=data5 ; end
data5 :
begin rs<=1; data<=one_6; next<=data6 ; end
data6 :
begin rs<=1; data<=one_7; next<=data7 ; end
data7 :
begin rs<=1; data<=one_8; next<=data8 ; end
data8 :
begin rs<=1; data<=one_9; next<=data9 ; end
data9 :
begin rs<=1; data<=one_10; next<=data10 ; end
data10 :
begin rs<=1; data<=one_11; next<=data11 ; end
data11 :
begin rs<=1; data<=one_12; next<=data12 ; end
data12 :
begin rs<=1; data<=one_13; next<=data13 ; end
data13 :
begin rs<=1; data<=one_14; next<=data14 ; end
data14 :
begin rs<=1; data<=one_15; next<=data15 ; end
data15 :
begin rs<=1; data<=one_16; next<=state5 ; end
state5:
begin rs<=0;data<=8'hC0; next<=data16; end //显示第二行
data16 :
begin rs<=1; data<=two_1; next<=data17 ; end
data17 :
begin rs<=1; data<=two_2; next<=data18 ; end
data18 :
begin rs<=1; data<=two_3; next<=data19 ; end
data19 :
begin rs<=1; data<=two_4; next<=data20 ; end
data20 :
begin rs<=1; data<=two_5; next<=data21 ; end
data21 :
begin rs<=1; data<=two_6; next<=data22 ; end
data22 :
begin rs<=1; data<=two_7; next<=data23 ; end
data23 :
begin rs<=1; data<=two_8; next<=data24 ; end
data24 :
begin rs<=1; data<=two_9; next<=data25 ; end
data25 :
begin rs<=1; data<=two_10; next<=data26 ; end
data26 :
begin rs<=1; data<=two_11; next<=data27 ; end
data27 :
begin rs<=1; data<=two_12; next<=data28 ; end
data28 :
begin rs<=1; data<=two_13; next<=data29 ; end
data29 :
begin rs<=1; data<=two_14; next<=data30 ; end
data30 :
begin rs<=1; data<=two_15; next<=data31 ; end
data31 :
begin rs<=1; data<=two_16; next<=scan ; end
scan : //交替更新第一行和第二行数据
begin
next<=state4;
end
default: next<=state0;
endcase
end
assign en=lcd_clk && en_sel;
assign rw=0;
endmodule |
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