library ieee; use ieee.std_logic_1164.all; entity m6 is port(clk:in std_logic; load:in std_logic; d:in std_logic; q ut std_logic); end m6; architecture behav of m6 is signal c0,c1,c2,c3,c4,c5,c6,c7:std_logic; begin process(clk,load) begin if clk'event and clk='1'then if(load='1'and d='1')then c7<='0'; c6<='0'; c5<='0'; c4<='0'; c3<='0'; c2<='0'; c1<='0'; c0<='1'; q<=c7; else c1<=c0; c2<=c1; c3<=c2; c4<=c3; c5<=c4; c6<=c5; c7<=c6; c0<=c7 xor c4 xor c3 xor c2; q<=c7; end if; end if; end process; end behav;
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