我写的一个VHDL程序，用simulator查看，发现输出没有变化
大虾看看哪里有问题？我是个新手
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity EL16 is
port(vid_in:in std_logic_vector(3 downto 0);
clk:in std_logic;
vs,hs,selftest ut std_logic;
vid_outut std_logic_vector(3 downto 0));
end EL16;
architecture rtl of EL16 is
type states is (st0,st1,st2,st3,st4);
signal current_state,next_state:states:=st0;
signal vid_temp:std_logic_vector(3 downto 0);
begin
com:process(current_state)
begin
case current_state is
when st0=>next_state<=st1;
vs<='1';
hs<='0';
selftest<='0';
when st1=>next_state<=st2;
vs<='1';
hs<='0';
selftest<='0';
when st2=>next_state<=st3;
vs<='1';
hs<='1';
selftest<='0';
when st3=>next_state<=st4;
vs<='1';
hs<='0';
selftest<='0';
vid_temp<=vid_in;
when st4=>vs<='0';
hs<='0';
selftest<='0';
vid_temp<=vid_in;
end case;
end process;
clock:process(clk,current_state)
VARIABLE cnt:integer RANGE 0 TO 3;
begin
if clk'event and clk='1' then
if current_state=st4 then
if cnt=3 then
cnt:=0;
current_state<=st1;
else
cnt:=cnt+1;
end if;
else
current_state<=next_state;
end if;
end if;
end process;
vid_out<=vid_temp;
end rtl; | 
