Verilog HDL HDL, Verilog

winner245

请问:  Verilog HDL中的wait语句如何使用?   谁能给我一个实例 ?

winner245

怎么只有人看没人回啊?
有没有人会啊?

gymdove

The wait statement will not block execution if its condition is true. If the condition is not true, it will wait until it becomes true.
Example:

module wait_example;
reg [7:0] a;
reg b;
initial begin
  wait (a==3)
      $display("not waiting for a==3 time %0d", $time);
  wait(b)
      $display("not waiting for b time %0d", $time);
  wait (a==4)
      $display("not waiting for a==4 time %0d", $time);
end
initial begin
  #3 a = 3;
    $display("value of a is now %0d at time %0d", a,$time);
  #1 a = 4;
    $display("value of a is now %0d at time %0d",a,$time);
  #1 b = 1;
    $display("value of b is now %0d at time %0d",b,$time);
end
endmodule