应该不难吧?
module BiDirRegs ( BIDIR1 ,BIDIR2 ,EN1 ,EN2 );
input EN1 ;
wire EN1 ;
input EN2 ;
wire EN2 ;
inout [7:0] BIDIR1 ;
wire [7:0] BIDIR1 ;
inout [7:0] BIDIR2 ;
wire [7:0] BIDIR2 ;
//}} End of automatically maintained section
assign BIDIR1 = ((EN1 == 1'b0) & (EN2 == 1'b1))? 8'bZZZZZZZZ : BIDIR2;
assign BIDIR2 = ((EN2 == 1'b0) & (EN1 == 1'b1))? 8'bZZZZZZZZ : BIDIR1;
// -- Enter your statements here -- //
endmodule |