有关数据类型的问题 类型, 数据

zj003_0

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; Entity kuozhan is port( sample : IN [I]std_logic_vector[/I](7 downto 0); clk: in std_logic; reset: in std_logic; enable: in std_logic; dataout0: out [I]std_logic_vector[/I](8 downto 0) ); end; Architecture kuozhan_behav of kuozhan is signal b0: std_logic_vector (8 downto 0); begin process(clk,reset) begin if reset='1' then b0<=(others=>'0'); elsif clk'event and clk='1' then if enable='1' then if sample(7)='0' then b0<="00" & sample(6 downto 0); else b0<="11" & sample(6 downto 0); end if; end if; end if; end process; dataout0<=b0; end; 我想问一下，上面程序中定义为std_logic_vector的数据类型为什么定义成signed的类型就不行呢，定义成signed类型前仿真总是不能运行，请大虾指教。