- UID
- 82798
- 性别
- 男
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这个东西这么老是整不好??
应该怎样把信号和输入输出联系起来??
大家看一下该怎么改??
跪谢了!!!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity splender is
port(clk,rst:in std_logic;
endin:in std_logic_vector(3 downto 0);
countut std_logic_vector(3 downto 0));
end splender;
architecture logic of splender is
signal state,nstate : std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst = '1' then
state<="0000";
elsif rising_edge(clk) then
state<=nstate;
end if;
end process;
process(state,endin)
begin
if state = endin then
state<="0001";
else
nstate<=state+"0001";
end if;
end process;
count<=state;
end logic;
[em06] |
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