vhdl程序举例-献给和我一样刚起步的GGMM[转帖] vhdl, GGMM, 转帖, 程序, 举例

vhdl程序举例-献给和我一样刚起步的GGMM 最高优先级编码器 LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity priority is port(I : in bit_vector(7 downto 0); --inputs to be prioritised A : out bit_vector(2 downto 0); --encoded output GS : out bit); --group signal output end priority; architecture v1 of priority is begin process(I) begin GS <= '1'; --set default outputs A <= "000"; if I(7) = '1' then A <= "111"; elsif I(6) = '1' then A <= "110"; elsif I(5) = '1' then A <= "101"; elsif I(4) = '1' then A <= "100"; elsif I(3) = '1' then A <= "011"; elsif I(2) = '1' then A <= "010"; elsif I(1) = '1' then A <= "001"; elsif I(0) = '1' then A <= "000"; else GS <= '0'; end if; end process; end v1; 8位想等比较器 -- 8-bit Identity Comparator -- uses 1993 std VHDL library IEEE; use IEEE.Std_logic_1164.all; entity HCT688 is port(Q, P : in std_logic_vector(7 downto 0); GBAR : in std_logic; PEQ : out std_logic); end HCT688; architecture VER1 of HCT688 is begin PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1'; end VER1; 三态总线 LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); sel : IN STD_LOGIC; my_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END prebus; ARCHITECTURE cpld OF prebus IS BEGIN my_out <= "ZZZZZZZZ" WHEN (sel = '1') ELSE my_in; END cpld; 双向总线 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); oe, clk : IN STD_LOGIC; inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0); outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END bidir; ARCHITECTURE cpld OF bidir IS SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores -- value from input. SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores BEGIN -- feedback value. PROCESS(clk) BEGIN IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops a <= inp; outp <= b; END IF; END PROCESS; PROCESS (oe, bidir) -- Behavioral representation BEGIN -- of tri-states. IF( oe = '0') THEN bidir <= "ZZZZZZZZ"; b <= bidir; ELSE bidir <= a; b <= bidir; END IF; END PROCESS; END cpld; 多路选择器 library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d: in std_logic_vector(3 downto 0); s: in std_logic_vector(1 downto 0); x: out std_logic_vector(3 downto 0)); end mux; architecture archmux of mux is begin mux4_1: process (a, b, c, d) begin if s = "00" then x <= a; elsif s = "01" then x <= b; elsif s = "10" then x <= c; else x <= d; end if; end process mux4_1; end archmux;