偶在做一个60进制的计数器 遇到了一个问题解决不了 哪位仁兄帮忙解决以下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcd60count is
port(clk,bcd1wr,bcd10wr,cin:in std_logic;
cout std_logic;
datain:in std_logic_vector(3 downto 0);
bcd1ut std_logic_vector(3 downto 0);
bcd10ut std_logic_vector(2 downto 0));
end bcd60count;
architecture rtl of bcd60count is
signal bcd1n:std_logic_vector(3 downto 0);
signal bcd10n:std_logic_vector(2 downto 0);
begin
bcd1<=bcd1n;
bcd10<=bcd10n;
process(clk,bcd1wr)
begin
if(bcd1wr='1')then
bcd1n<=datain(3 downto 0);
elsif(clk'event and clk='1')then
if(cin='1')then
if(bcd1n=9)then
bcd1n<="0000";
else
bcd1n<=bcd1n+1;
end if;
end if;
end if;
end process;
process(clk,bcd10wr)
begin
if(bcd10wr='1')then
bcd10n<=datain(2 downto 0);
elsif (clk'event and clk='1')then
if(cin='1' and bcd1n=9)then
if(bcd10n=5)then
bcd10n<="000";
else
bcd10n<=bcd10n+1;
end if;
end if;
end if;
end process;
process(bcd10n,bcd1n,cin)
begin
if(cin='1' and bcd1n=9 and bcd10n=5)then
co<='1';
else
co<='0';
end if;
end process;
end rtl;
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