- UID
- 856476
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阻塞赋值
=
非阻塞赋值 <=
接触数字逻辑好几年了,经常被问到Verilog阻塞赋值和非阻塞赋值问题,一开始就是将书上说的什么阻塞赋值就是先计算赋值号右边的表达式,等计算完了再赋值,并且前面的语句对后面有阻塞作用,即后面等式的执行要等前面执行完再执行;非阻塞赋值是先赋值再计算,语句的执行顺序和语句的先后关系无关。阻塞赋值类似于C语言,一句一句往下顺序执行,非阻塞赋值更接近于硬件原理,体现并行计算。这样理解没有任何问题,但是作为硬件描述语言,阻塞赋值和非阻塞赋值体现的是综合器的综合原理,只有将其放在综合出的硬件电路中才有意义。
最近看了一本老外的书,介绍Verilog综合的,书中对阻塞赋值(blocking assignment)和非阻塞赋值(non-blocking assignment)的描述是这样的:
In a blocking assignment, the assignment to the left hand side target completes before the next statement in the sequential block is ,executed. In a non-blocking assignment, the assignment to the left hand side target is scheduled for the end of the simulation cycle before the next statement is, executed.
具体意思大家自己理解,只有真正自己理解了,那么也就弄清楚两者的真正区别了。
看一个例子,例子由synplify综合:
module block_non_block(
input clk,rst,
input strobe_a,
input xflag,
input mask,
output rightshift,
output selectfirst,
output checkstop
);
reg rightshift;
reg selectfirst;
reg checkstop;
always@(posedge clk)
begin
rightshift <= rst & strobe_a;
selectfirst <= rightshift| xflag;
checkstop <= selectfirst ^ mask;end
end
endmodule
module block_non_block(
input clk,rst,
input strobe_a,
input xflag,
input mask,
output rightshift,
output selectfirst,
output checkstop
);
reg rightshift;
reg selectfirst;
reg checkstop;
always@(posedge clk)
begin
rightshift = rst & strobe_a;
selectfirst <= rightshift| xflag;
checkstop <= selectfirst ^ mask;end
end
endmodule
module block_non_block(
input clk,rst,
input strobe_a,
input xflag,
input mask,
output rightshift,
output selectfirst,
output checkstop
);
reg rightshift;
reg selectfirst;
reg checkstop;
always@(posedge clk)
begin
rightshift = rst & strobe_a;
selectfirst = rightshift| xflag;
checkstop = selectfirst ^ mask;end
end
endmodule
这样语句对应正在的电路,相信大家会更清楚的理解阻塞和非阻塞的区别。
参考文献是:
Verilog HDL synthesis A Practical Primer J.Bhasker |
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