我是初学者,要实现一个fifo的功能,程序读写时钟不一致,读比写的时钟要慢一些,自己动手编了下面程序,运行了以后有错误,哪位大虾帮我看看,谢了.运行警告错误如下:
WARNING:Xst:528 - Multi-source in Unit <fifo1> on signal <counter1_3> not replaced by logic
Sources are: counter1_ren_3 , counter1_3
WARNING:Xst:528 - Multi-source in Unit <fifo1> on signal <counter1_0> not replaced by logic
Sources are: counter1_ren_0, counter1_0
WARNING:Xst:528 - Multi-source in Unit <fifo1> on signal <counter1_1> not replaced by logic
Sources are: counter1_ren_1, counter1_1
WARNING:Xst:528 - Multi-source in Unit <fifo1> on signal <counter1_2> not replaced by logic
Sources are: counter1_ren_2, counter1_2
ERROR:Xst:415 - Synthesis failed
CPU : 2.63 / 4.14 s | Elapsed : 2.00 / 4.00 s
-->
Total memory usage is 51256 kilobytes
module fifo1(clk,reset,datain,dataout1,full1,empty1);//16*4 fifo
input clk,reset; //
input [3:0] datain; //数据输入
output [3:0] dataout1; //存储器数据输出
output empty1,full1; //存储单元空、满标志位
reg [3:0] dataout1;
reg[3:0] read_ptr1,write_ptr1; //读写地址指针
reg[3:0] counter1; //记数器
reg empty1,full1;
reg [3:0] ram1 [0:15];//16*4存储单元
wire clk1;
wire [25:0] d;
assign d =26'd00_005; //d为分频数
Freq_Div myFreq_Div1 (
.Clk_Sys(clk),
.Div(d),
.Reset(reset),
.Clk_User(clk1)
);
always @(posedge clk) //写存储单元
begin
if(reset)
begin
write_ptr1=2'b00;
counter1=2'b00;
full1=0;
end
else if(counter1<15)
begin
ram1[write_ptr1]=datain; //将数据输入存储单元
counter1=counter1+1; //每写入一个数计数器加一
write_ptr1=(write_ptr1==15)?0:write_ptr1+1; //写满返回首地址，否则写地址指针加一
end
else
begin
full1=1;
counter1=15; //存储器满标志位
end
end
always @(posedge clk1) //读子程序
if(reset)
begin
read_ptr1=2'b00;
dataout1=2'b00;
empty1=1;
end
else if(counter1!=0)
begin
dataout1=ram1[read_ptr1];
counter1=counter1-1;
read_ptr1=(read_ptr1==15)?0:read_ptr1+1;
end
else
empty1=1; //存储器空
endmodule | 
