我在QUARTUSII6.0用VHDL编程,每次只要程序中含有 + 、-、*、/ ,编译时都会报类似的错误,如下面这个程序: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity adder is port( in1 : bit_vector; in2 : bit_vector; cnt1 : bit; pout : out bit_vector); end entity adder; architecture func of adder is begin process(cnt1) begin if(cnt1='1') then pout<=in1 + in2; end if; end process; end architecture func; 每次编译时总是出现这样的错误提示: Error (10327): VHDL error at adder.vhd(15): can't determine definition of operator ""+"" -- found 0 possible definitions Error (10523): Ignored construct func at adder.vhd(11) due to previous errors
如果把程序中的“+”换成“*”或者“-”,编译时会把错误中的operator ""+"" 改成operator ""*""和operator ""-"",请高手指点一下出错的原因。谢谢了 |