主程序 module add_8bit(sum,cout,a,b,co,clk); output [7:0] sum; output cout; input [7:0] a,b; input co,clk; reg cout,lc0,lc1,lc2,lc3; reg [1:0] ls1,la3,lb3; reg [3:0] ls2,la2,lb2; reg [5:0] ls3,la1,lb1; reg [7:0] la0,lb0,ls4,sum; always @ (clk) begin lc0=co; la0=a; lb0=b; end always@(clk) begin {lc1,ls1}=lc0+la0[1:0]+lb0[1:0]; la1=la0[7:2]; lb1=lb0[7:2]; end always@(clk) begin {lc2,ls2}={lc1+la1[1:0]+lb1[1:0],ls1}; la2=la1[5:2]; lb2=lb1[5:2]; end always@(clk) begin {lc3,ls3}={lc2+la2[1:0]+lb2[1:0],ls2}; la3=la2[3:2]; lb3=lb2[3:2]; end always@(clk) begin {cout,sum}={lc3+la3[1:0]+lb3[1:0],ls3}; end endmodule 测试程序 module tp_v; // Inputs reg [7:0] a; reg [7:0] b; reg co; reg clk; // Outputs wire [7:0] sum; wire cout; parameter Delay=100; // Instantiate the Unit Under Test (UUT) add_8bit uut ( .sum(sum), .cout(cout), .a(a), .b(b), .co(co), .clk(clk) ); initial begin // Initialize Inputs a = 120; b = 111; co = 1; clk = 0; // Wait 100 ns for global reset to finish #1000 $finish; // Add stimulus here end always #(Delay/2) clk=~clk; endmodule
[此贴子已经被作者于2007-5-29 10:09:47编辑过] |