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-- Company: njupt
-- Engineer: --
-- Create Date: 14:10:17 07/27/2007
-- Design Name: dengjingdupinlvji
-- Module Name: shishi - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all; entity yuanchengxv is
Port ( chekf,finput,choice : in std_logic;
start,clrtrig,fstd,tf : in std_logic;
sel : in std_logic_vector(2 downto 0);
Q1,Q2:inout std_logic_vector(31 downto 0);
oo : out std_logic_vector(7 downto 0);
eend : out std_logic;
endd : out std_logic);
end yuanchengxv; architecture art of yuanchengxv is component fin is
port (chkf,fin,chois: in std_logic;
fout: out std_logic);
end component ;
component contrl is
port (fin,start,clr,fsd:in std_logic;
clk1,eend,clk2,clrc ut std_logic);
end component ; component cnt is
port(clk,clr:in std_logic;
Q: out std_logic_vector(31 downto 0));
end component ;
component contrl2 is
port(fin,start,clr: in std_logic;
endd,pul : out std_logic);
end component;
component gate is
port (clk2,fsd,cnl,pul: in std_logic;
clkout: out std_logic);
end component ;
signal inclk: std_logic;
signal fout,clrc: std_logic;
signal clk1,clk2,clkout,pul: std_logic;
-- signal Q1,Q2: std_logic_vector(31 downto 0);
begin
oo<= Q1 (7 downto 0) when sel="000"
else Q1 (15 downto 8) when sel="001" else
Q1 (23 downto 16) when sel="010" else
Q1 (31 downto 24) when sel="011" else
Q2 (7 downto 0) when sel="100" else
Q2 (15 downto 8) when sel="101" else
Q2 (23 downto 16) when sel="110" else
Q2 (31 downto 24) when sel="111" else
"00000000"; fenpin: process(fstd) is
begin
if fstd'event and fstd ='1'then
inclk <= not inclk;
end if;
end process fenpin; fch: fin port map (chkf => chekf, fin => finput, chois => choice, fout => fout);
con: contrl port map (fin => fout,start => start, clr=>clrtrig, fsd => inclk,
clk1 => clk1, eend => eend,clk2 => clk2, clrc => clrc);
cont1: cnt port map (clk => clk1,clr => clrc, Q => Q1);
cont2: cnt port map (clk => clkout,clr => clrc, Q => Q2);
con2: contrl2 port map (fin => fout,start => start,clr => clrc,pul => pul,endd => endd);
gate1: gate port map (clk2 => clk2,fsd=>inclk,cnl=>tf,pul => pul,clkout => clkout);
end art;
library IEEE; --计数模块
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt is
port(clk,clr:in std_logic;
Qut std_logic_vector(31 downto 0));
end entity cnt; architecture art of cnt is
signal cnt:std_logic_vector(31 downto 0);
begin
process (clk,clr) is
begin
if clr='1' then cnt<="00000000000000000000000000000000";
elsif clk'event and clk='1' then cnt <= cnt+1;
end if;
end process;
Q<=cnt;
end art;
--测频，周期控制模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity contrl is
port(fin,start,clr,fsd:in std_logic;
clk1,eend,clk2,clrc: out std_logic);
end contrl; architecture art of contrl is
signal QQ1:std_logic;
begin
process(fin,clr,start) is
begin
if clr='1' then QQ1<='0';
elsif fin'event and fin='1' then QQ1<=start;
end if;
end process;
clrc<=clr;
eend<=QQ1;
clk1<=fin and QQ1;
clk2<=fsd and QQ1;
end art; library IEEE; --测脉宽、占空比模块
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity contrl2 is
port(fin,start,clr:in std_logic;
endd,pulut std_logic);
end contrl2; architecture art of contrl2 is
signal QQ: std_logic_vector(3 downto 1);
signal A0,B0,C0,F2:std_logic;
signal S: std_logic_vector(1 downto 0);
begin
S(0)<=QQ(3);
S(1)<=QQ(2);
process (start ,S) is
begin
if start='1' then F2<=fin;
else F2<=not fin;
end if;
if S=2 then pul<='1' ;
else pul<='0';
end if;
if S=3 then endd<='1';
else endd<='0';
end if;
end process;
A0<=F2 and QQ(1);
B0<= not A0;
C0<= not F2;
process(C0,clr) is
begin
if clr='1' then QQ(1)<='0';
elsif C0'event and C0='1' then QQ(1)<='1';
end if;
end process;
process (A0,clr) is
begin
if clr='1' then QQ(2)<='0';
elsif A0'event and A0='1' then QQ(2)<='1';
end if;
end process; process (B0,clr) is
begin
if clr='1' then QQ(3)<='0';
elsif B0'event and B0='1' then QQ(3)<='1';
end if;
end process;
end art; library IEEE; --自校/测试频
use IEEE.STD_LOGIC_1164.ALL; entity fin is
port (chkf,fin,chois:in std_logic;
foutut std_logic);
end fin; architecture rtl of fin is
begin
fout<=(fin and chois) or (chkf and not chois);
end rtl; library IEEE; --计数器二频率切换模块
use IEEE.STD_LOGIC_1164.ALL;
entity gate is
port (clk2,fsd,cnl,pul:in std_logic;
clkoutut std_logic);
end gate; architecture art of gate is
begin
process(clk2,pul,fsd,cnl) is
begin
if cnl='0' then clkout<=clk2;
else clkout<=pul and fsd;
end if;
end process;
end art; 我这个程序当SEL大于3时，调不出数据，CNT2模块不计数，请高手帮我看看那
[此贴子已经被作者于2007-8-17 19:40:44编辑过] | 
