Development Kit Contents
The SOCkit-Cyclone EP1C6 Nios/LVDS Evaluation Kit (shown in Figure 1) includes the following:
SOCkit evaluation board (shown in Figure 2)
Eight LVDS channels available for loop-back or board-to-board testing (configurable data rate)
LVDS pattern generation and detection with byte-error rate testing
32-bit Nios processor (OpenCore™ Plus evaluation edition)
Nios software image stored on EPCS4 flash device (selected from LCD menu).
Configurable Nios software boot using GERMS RS-232 monitor or EPCS4 image copy to SRAM (configurable via dip-switch)
Nios program execution from external 128Kx8-bit SRAM
EPCS4 non-volatile flash data storage
LCD menu selection using two push-buttons
Six user-controllable LEDs
24-Mhz oscillator
Four-position dip switch
Reset and voltage monitor IC with reset push button
Joint Test Action Group (JTAG) header
Active serial memory interface (ASMI) header
94 FPGA I/O pins accessible on 0.1” pin headers
16-character x 2-line LCD display
14-pin LCD ribbon cable
LVDS patch cable
5-V DC/2A switching power supply
DB-9 RS232 cable
Altera ByteBlaster™ II FPGA programmer
Altera Quartus II Software Starter Suite CD-ROM
SOCkit reference design and data files CD-ROM |
