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- UID
- 818940
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ERROR: (SdfError)Error while parsing sdf file "netgen/par/top_timesim.sdf" Line 1: syntax error, unexpected IDENTIFIER, expecting DELAYFILE.
之前顺利通过了Synthesize - XST, 也通过了Implement Design, 当然也通过了Generate Programming File 然后我进行了Post-Route仿真，ISim也已经启动了，但就是没东西，什么都没有，下面的控制台窗口有上面那句话。完整的信息如下：
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WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
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This is a Full version of ISim.
Time resolution is 10 fs
Simulator is doing circuit initialization process.
ERROR: (SdfError)Error while parsing sdf file "netgen/par/sp605_demo_20b_timesim.sdf" Line 1: syntax error, unexpected IDENTIFIER, expecting DELAYFILE.
WARNING: ISim could not properly annotate the SDF timing delay information.
Attribute Syntax Error : The calculation of VCO frequency=300.000000 Mhz. This exceeds the permitted VCO frequency range of 400.000000 Mhz to 1440.000000 Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range.
Stopped at time : 0 fs : File "v:/hipsBuilds/L_hips_v16.0/rst/hips/gtpa1_dual/GTPA1_DUAL_all_enc.v" Line 61595
ISim>
其中我要补充说明的是Implement Design步骤产生的两个文件（其中一个就是上面报错提到的）：top_timesim.sdf和top_timesim.v打开是乱码，而其他工程下的两个文件不是乱码，不知道这么是怎么回事？
上述控制台信息中还有第二个错误，有碰到的大虾指点下啊，最后说下，我是个菜鸟，入门才一个星期...网上也找不到类似的东西，所以知道发帖求救了 |
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