silverwolf

module clock_gen;

reg clock;

//Initialize clock at time zero
initial
clock = 1'b0;

//Toggle clock every half cycle (time period = 20)
always
#10 clock = ~clock;

initial
#1000 $finish;

endmodule

silverwolf

2.block

module dummy;
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;


//All behavioral statements must be inside an initial or always block
initial
begin
        x = 0; y = 1; z = 1; //Scalar assignments
        count = 0; //Assignment to integer variables
        reg_a = 16'b0; reg_b = reg_a; //initialize vectors

        reg_a[2] = #15 1; //Bit select assignment with delay
        reg_b[15:13] = #10 {x, y, z};//Assign result of concatenation to
                                     // part select of a vector
        count = count + 1; //Assignment to an integer (increment)
end

initial
        $monitor($time,
        " x = %b, y = %b, z = %b, count = %0d, reg_a = %x, reg_b = %x",
    x, y, z, count, reg_a, reg_b);

endmodule

silverwolf

3.counter

//Binary counter
module counter(Q , clock, clear);

// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;

always @( posedge clear or negedge clock)
begin
if (clear)
Q = 4'd0;
else
//Q = (Q + 1) % 16;
Q = (Q + 1) ;
end

endmodule

// Top level stimulus module
module stimulus;

// Declare variables for stimulating input
reg CLOCK, CLEAR;
wire [3:0] Q;

initial
$monitor($time, " Count Q = %b Clear= %b", Q[3:0],CLEAR);

initial
$gr_waves( "clk", CLOCK,
"Clear", CLEAR,
"Q", Q[3:0],
"Q0", Q[0],
"Q1", Q[1],
"Q2", Q[2],
"Q3", Q[3]);

// Instantiate the design block counter
counter c1(Q, CLOCK, CLEAR);

// Stimulate the Clear Signal
initial
begin
CLEAR = 1'b1;
#34 CLEAR = 1'b0;
#200 CLEAR = 1'b1;
#50 CLEAR = 1'b0;
end

// Setup the clock to toggle every 10 time units
initial
begin
CLOCK = 1'b0;
forever #10 CLOCK = ~CLOCK;
end

// Finish the simulation at time 200
initial
begin
#400 $stop;
end

endmodule

silverwolf

4. for

module counter;

integer count;

initial
for ( count=0; count < 128; count = count + 1)
$display("Count = %d", count);

endmodule

silverwolf

5. forever

module synchronize;

//Example 2: Synchronize two register values at every positive edge of
//clock
reg clock;
reg x, y;

initial
begin
clock = 1'b0;
x = 1'b0;
y = 1'b0;
#100000 $finish;
end

always #5 clock = ~clock;
always #11 y = ~y;

initial
forever @(posedge clock) x = y;

endmodule

silverwolf

6.fulladd

/ Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;

// Specify the function of a full adder
assign #2 {c_out, sum} = a + b + c_in;

endmodule

// Define the stimulus (top level module)
module stimulus;

// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4
fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);


// Setup the monitoring for the signal values
initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b,, C_OUT= %b, SUM= %b\n",
A, B, C_IN, C_OUT, SUM);
end

silverwolf

7.func2 //Define a module which contains the function shift module shifter; //Left/right shifter `define LEFT_SHIFT 1'b0 `define RIGHT_SHIFT 1'b1 reg [31:0] addr, left_addr, right_addr; reg control; initial begin $monitor("%0d left= %h right = %h addr = %h", $time, left_addr, right_addr, addr); #1 addr = 32'h3456_789a; #10 addr = 32'hc4c6_78ff; #10 addr = 32'hff56_ff9a; #10 addr = 32'h3faa_aaaa; end //Compute the right and left shifted values whenever //a new address value appears always @(addr) begin //call the function defined below to do left and right shift. left_addr = shift(addr, `LEFT_SHIFT); right_addr = shift(addr, `RIGHT_SHIFT); end //define shift function. The output is a 32-bit value. function [31:0] shift; input [31:0] address; input control; begin //set the output value appropriately based on a control signal. shift = (control == `LEFT_SHIFT) ?(address << 1) : (address >> 1); end endfunction endmodule

silverwolf

8.imp_del

module implicit_delay (out, in1, in2);

output out;
input in1, in2;

wire #10 out = in1 & in2; // Delay in a continuous assign

endmodule

module stimulus;

wire OUT;
reg IN1, IN2;
initial
begin
IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;

#40 IN1 = 0;

#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end

initial
$gr_waves("out", OUT, "in1", IN1, "in2", IN2);

implicit_delay rd1(OUT, IN1, IN2);

endmodule

silverwolf

9.initial

module stimulus;

reg x,y, a,b, m;

initial
m = 1'b0; //single statement; does not need to be grouped

initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end

initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end

initial
#50 $finish;

endmodule

silverwolf

10.momory
module test;

reg [7:0] memory[0:7]; //declare an 8 bit memory with 8 locations
integer i;

initial
begin
//read memory file. address locations given in memory
$readmemb("init.dat", memory);
//display contents of initialized memory
for(i=0; i < 8; i = i + 1)
$display("Memory [%0d] = %b", i, memory);
end

endmodule

silverwolf

11.mux1
/ 4-to-1 multiplexer. Port list is taken exactly from
// the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;

assign out = (~s1 & ~s0 & i0) |
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3) ;


endmodule

// Define the stimulus module (no ports)
module stimulus;

// Declare variables to be connected
// to inputs
reg IN0, IN1, IN2, IN3;
reg S1, S0;

// Declare output wire
wire OUTPUT;

// Instantiate the multiplexer
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

// Stimulate the inputs
initial
begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);


// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end

endmodule

silverwolf

12.mux2
// 4-to-1 multiplexer. Port list is taken exactly from
// the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;

assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;

endmodule

// Define the stimulus module (no ports)
module stimulus;

// Declare variables to be connected
// to inputs
reg IN0, IN1, IN2, IN3;
reg S1, S0;

// Declare output wire
wire OUTPUT;

// Instantiate the multiplexer
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

// Stimulate the inputs
initial
begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);


// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end

endmodule

silverwolf

13.mux4
// 4-to-1 multiplexer. Port list is taken exactly from
// the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
//output declared as register
reg out;

//recompute the signal out if any input signal changes.
//All input signals that cause a recomputation of out to
//occur must go into the always @(...)
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end

endmodule

// Define the stimulus module (no ports)
module stimulus;

// Declare variables to be connected
// to inputs
reg IN0, IN1, IN2, IN3;
reg S1, S0;

// Declare output wire
wire OUTPUT;

// Instantiate the multiplexer
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

// Stimulate the inputs
initial
begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);


// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end

endmodule

silverwolf

14.repeat
//Illustration 2 : Data buffer module example
//After it receives a data_start signal.
//Reads data for next 8 cycles.

module data_buffer(data_start, data, clock);

parameter cycles = 8;
input data_start;
input [15:0] data;
input clock;

reg [15:0] buffer [0:7];
integer i;

always @(posedge clock)
begin
if(data_start) //data start signal is true
begin
i = 0;
repeat(cycles) //Store data at the posedge of next 8 clock
//cycles
begin
@(posedge clock) buffer = data; //waits till next
// posedge to latch data
i = i + 1;
end
end
end

endmodule

silverwolf

15.sig-ctrl
`define TRUE 1'b1
`define FALSE 1'b0
`define RED 2'd0
`define YELLOW 2'd1
`define GREEN 2'd2

//State definition HWY CNTRY
`define S0 3'd0 //GREEN RED
`define S1 3'd1 //YELLOW RED
`define S2 3'd2 //RED RED
`define S3 3'd3 //RED GREEN
`define S4 3'd4 //RED YELLOW

//Delays
`define Y2RDELAY 3 //Yellow to red delay
`define R2GDELAY 2 //Red to Green Delay

module sig_control
(hwy, cntry, X, clock, clear);

//I/O ports
output [1:0] hwy, cntry;
//2 bit output for 3 states of signal
//GREEN, YELLOW, RED;
reg [1:0] hwy, cntry;
//declare output signals are registers

input X;
//if TRUE, indicates that there is car on
//the country road, otherwise FALSE

input clock, clear;


//Internal state variables
reg [2:0] state;
reg [2:0] next_state;

//Signal controller starts in S0 state
initial
begin
state = `S0;
next_state = `S0;
hwy = `GREEN;
cntry = `RED;
end

//state changes only at positive edge of clock
always @(posedge clock)
state = next_state;

//Compute values of main signal and country signal
always @(state)
begin
case(state)
`S0: begin
hwy = `GREEN;
cntry = `RED;
end

`S1: begin
hwy = `YELLOW;
cntry = `RED;
end
`S2: begin
hwy = `RED;
cntry = `RED;
end
`S3: begin
hwy = `RED;
cntry = `GREEN;
end
`S4: begin
hwy = `RED;
cntry = `YELLOW;
end
endcase
end


//State machine using case statements
always @(state or clear or X)
begin
if(clear)
next_state = `S0;
else
case (state)
`S0: if( X)
next_state = `S1;
else
next_state = `S0;
`S1: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state = `S2;
end
`S2: begin //delay some positive edges of clock
repeat(`R2GDELAY) @(posedge clock)
next_state = `S3;
end
`S3: if( X)
next_state = `S3;
else
next_state = `S4;
`S4: begin //delay some positive edges of clock
repeat(`Y2RDELAY) @(posedge clock) ;
next_state = `S0;
end
default: next_state = `S0;
endcase
end

endmodule

//Stimulus Module
module stimulus;

wire [1:0] MAIN_SIG, CNTRY_SIG;
reg CAR_ON_CNTRY_RD;
//if TRUE, indicates that there is car on
//the country road
reg CLOCK, CLEAR;

//Instantiate signal controller
sig_control SC(MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD, CLOCK, CLEAR);


//Setup monitor
initial
$monitor($time, " Main Sig = %b Country Sig = %b Car_on_cntry = %b",
MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD);

//Setup waves
initial
$gr_waves( "CLOCK", CLOCK,
"CAR", CAR_ON_CNTRY_RD,
"CLEAR", CLEAR,
"MAIN", MAIN_SIG,
"CNTRY", CNTRY_SIG);

//setup clock
initial
begin
CLOCK = `FALSE;
forever #5 CLOCK = ~CLOCK;
end

//control clear signal
initial
begin
CLEAR = `TRUE;
repeat (5) @(negedge CLOCK);
CLEAR = `FALSE;
end

//apply stimulus
initial
begin
CAR_ON_CNTRY_RD = `FALSE;

#200 CAR_ON_CNTRY_RD = `TRUE;
#100 CAR_ON_CNTRY_RD = `FALSE;

#200 CAR_ON_CNTRY_RD = `TRUE;
#100 CAR_ON_CNTRY_RD = `FALSE;

#200 CAR_ON_CNTRY_RD = `TRUE;
#100 CAR_ON_CNTRY_RD = `FALSE;

#100 $stop;
end


endmodule