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- UID
- 852722
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// UART RX Logic
Always @ (Posedge Rxclk Or Posedge Reset)
If (Reset) Begin
Rx_reg <= 0;
Rx_data <= 0;
Rx_sample_cnt <= 0;
Rx_cnt <= 0;
Rx_frame_err <= 0;
Rx_over_run <= 0;
Rx_empty <= 1;
Rx_d1 <= 1;
Rx_d2 <= 1;
Rx_busy <= 0;
End Else Begin
// Synchronize The Asynch Signal
Rx_d1 <= Rx_in;
Rx_d2 <= Rx_d1;
// Uload The Rx Data
If (Uld_rx_data) Begin
Rx_data <= Rx_reg;
Rx_empty <= 1;
End
// Receive Data Only When Rx Is Enabled
If (Rx_enable) Begin
// Check If Just Received Start Of Frame
If (!Rx_busy && !Rx_d2) Begin
Rx_busy <= 1;
Rx_sample_cnt <= 1;
Rx_cnt <= 0;
End
// Start Of Frame Detected, Proceed With Rest Of Data
If (Rx_busy) Begin
Rx_sample_cnt <= Rx_sample_cnt + 1;
// Logic To Sample At Middle Of Data
If (Rx_sample_cnt == 7) Begin
If ((Rx_d2 == 1) && (Rx_cnt == 0)) Begin
Rx_busy <= 0;
End Else Begin
Rx_cnt <= Rx_cnt + 1;
// Start Storing The Rx Data
If (Rx_cnt > 0 && Rx_cnt < 9) Begin
Rx_reg[Rx_cnt - 1] <= Rx_d2;
End
If (Rx_cnt == 9) Begin
Rx_busy <= 0;
// Check If End Of Frame Received Correctly
If (Rx_d2 == 0) Begin
Rx_frame_err <= 1;
End Else Begin
Rx_empty <= 0;
Rx_frame_err <= 0;
// Check If Last Rx Data Was Not Unloaded,
Rx_over_run <= (Rx_empty) ? 0 : 1;
End
End
End
End
End
End
If (!Rx_enable) Begin
Rx_busy <= 0;
End
End |
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