ads1204 基于fpga的sinc3滤波

yuyang911220

上图是我用vhdl语言在quartus 软件内绘制的针对ads1204的输出数据滤波模块，图中ADS1204_OUT_A  代表芯片的数据输出口，ADS1204_CLKOUT 代表芯片输出时钟，fredivn表示256分频即起到OSR=256的作用，sinc_1表示sinc3滤波。请问设计思路是否正确？我测试的结果是经过滤波后输出数据变化非常大，不知道问题出在哪里，请指教！
附件vhdl代码：
【fredivn】
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
port (clk:in std_logic;
outclkut std_logic);
end fredivn;
architecture rtl of fredivn is
signal count:integer:=0;
begin
process(clk)
begin
if(clk'event and clk='1') then
if(count=255)then
count<=0;
else
count<=count+1;
if count<128 then
outclk<='0';
else
outclk<='1';
end if;
end if;
end if;
end process;
end rtl;
【sinc3】
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity Sinc_1 is
port(RESN, MOUT, MCLK, CNR : in std_logic;
CN5 : out std_logic_vector(24 downto 0));
end Sinc_1;

architecture RTL of Sinc_1 is
signal Z1 : std_logic_vector(24 downto 0);
signal Z2 : std_logic_vector(24 downto 0);
signal Z3 : std_logic_vector(24 downto 0);
signal Z4 : std_logic_vector(24 downto 0);
signal Z5 : std_logic_vector(24 downto 0);
signal Z6 : std_logic_vector(24 downto 0);
signal Z7 : std_logic_vector(24 downto 0);
begin

process(MCLK, RESN)
begin
if RESN = '0' then
Z1 <= (others => '0');
Z2 <= (others => '0');
Z3 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
Z1 <= Z1 + MOUT;
Z2 <= Z2 + Z1;
Z3 <= Z3 + Z2;
end if;
end process;

process(CNR, RESN)
begin
if RESN = '0' then
Z4 <= (others => '0');
Z5 <= (others => '0');
Z6 <= (others => '0');
Z7 <= (others => '0');
elsif CNR'event and CNR = '1' then
Z4 <= Z3;
Z5 <= Z3 - Z4;
Z6 <= Z3 - Z4 - Z5;
Z7 <= Z3 - Z4 - Z5 - Z6;
end if;
end process;

CN5<= Z7;

end RTL;