程序问题~~
我练习用COMPONENT元件例化，可写出来的程序不能正确锁存，也是373的
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shaoxie373 IS
PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EN0,EN1,EN2,EN3,EN4,EN5,EN6:IN STD_LOGIC;
G:IN STD_LOGIC;
P1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P4:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P6:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
P7:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END shaoxie373;
ARCHITECTURE structure OF shaoxie373 IS
COMPONENT three
PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EN:IN STD_LOGIC;
G:IN STD_LOGIC;
P:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
BEGIN
U1:three
PORT MAP(D,EN0,G,P1);
U2:three
PORT MAP(D,EN1,G,P2);
U3:three
PORT MAP(D,EN2,G,P3);
U4:three
PORT MAP(D,EN3,G,P4);
U5:three
PORT MAP(D,EN4,G,P5);
U6:three
PORT MAP(D,EN5,G,P6);
U7:three
PORT MAP(D,EN6,G,P7);
END structure;
--373描述
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY three IS
PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EN:IN STD_LOGIC;
G:IN STD_LOGIC;
P:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END three;
ARCHITECTURE struct OF three IS
SIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(EN)
BEGIN
IF(G='1')THEN
P<="ZZZZZZZZ";
ELSIF(EN='1')THEN
P<=D;
END IF;
END PROCESS;
END struct;
