各位大侠,请帮忙看看这段程序。我想以1s为周期,每1s内若无触发信号(对触发信号trigger的上升沿检测)则输出为0,有触发信号时输出为1.这段程序编译能通过,但不论仿真还是下到FPGA板子上都不正常工作,实在想不明白为什么,请各位大侠指教。 library ieee; use ieee.std_logic_1164.all; entity testchufa is port(trigger:in std_logic; clk:in std_logic; endisp ut std_logic:='0'); end; architecture one of testchufa is signal i:integer :=0; begin process(clk) begin if clk'event and clk='1' then i<=i+1; if i=50000000 then i<=0; end if; end if; end process; process(i,trigger ) variable num:integer:=0; begin if trigger'event and trigger='1' then if i<50000000 then num:=num+1; end if; end if;
if i=50000000 then if num=0 then endisp<='0'; else endisp<='1'; end if; num:=0; end if; end process; end one; |