大虾们救命啊~! 大虾, 救命

lishengwen

这是我写的count16程序,但是不能仿真,老师说要加reset 但是我不会~!请高手帮我修改下~!谢谢~! library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity count16 is port(clk:in std_logic; D,C,B,Aut std_logic); end count16; architecture Behavioral of count16 is signal count_4:std_logic_vector(3 downto 0); begin process(clk) --进程敏感信号 begin if(clk'event and clk='1') then --时钟上升沿触发 if(count_4="1111") then count_4<="0000"; else count_4<=count_4+1; end if; end if; end process; D<=count_4(0); --最低位从D输出 C<=count_4(1); --次低位从C输出 B<=count_4(2); --次高位从B输出 A<=count_4(3); --最高位从A输出 end Behavioral; 先在这里谢谢大虾们了~! 我是刚刚学这个的,请不要笑话~~~~~~!!!