这是我写的四路同步复接器的程序,但是编译都编译不起~!
请大虾们帮我修改修改~~!!!!!!!!
我只有2天就要交论文了,所以请大家多帮帮忙,感激不尽
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.AL.0;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--lirary UNISIM;
--use UNISIM.VComponents.all;
entity fujieqi is --复接器实体名
port(clk,ena,a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,c0,c1,c2,c3,c4,c5,
c6,c7,d0,d1,d2,d3,d4,d5,d6,d7:in std_logic;
s0,s1,s2,s3,fujiout ut std_logic);
end fujieqi;
architecture Behavioral of fujieqi is
component count16 --调用计数器
port(clk:in std_logic;
D,C,B,Aut std_logic);
end component;
component neimacs0 --调用内码产生器
port(in0_8,in0_7,in0_6,in0_5,in0_4,in0_3,in0_2,in0_1,
K3,K2,K1,sx0:in std_logic;
out0ut std_logic);
end component;
component shixusuccessful --调用时序发生器
port(B:in std_logic;
S3,S2,S1,S0ut std_logic);
end component;
component men --调用门器件
port(in1 :in std_logic;
out1 ut std_logic);
end component;
component andmen --调用四与门
port(in1,in2,in3,in4:in std_logic;
outp: out std_logic);
end component;
component djhlatch --调用D触发器
PORT (D,ena:IN std_logic;
q1: out std_logic);
end component;
signal w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,
w12,w13,w14,w15,w16:std_logic; --信号赋值语句
begin
m1:neimacs0 port map(in0_1=>a0,in0_2=>a1, --以下为例化语句
in0_3=>a2,in0_4=>a3,in0_5=>a4,in0_6=>a5,
in0_7=>a6,in0_8=>a7,K3=>w3,K2=>w2,K1=>w1,sx0=>w4,out0=>w15);
m2:neimacs0 port map(in0_1=>b0,in0_2=>b1,in0_3=>b2,in0_4=>b3,
in0_5=>b4,in0_6=>b5,in0_7=>b6,in0_8=>b7,K3=>w3,K2=>w2,
K1=>w1,sx0=>w5,out0=>w14);
m3:neimacs0 port map(in0_1=>c0,in0_2=>c1,in0_3=>c2,in0_4=>c3,
in0_5=>c4,in0_6=>c5,in0_7=>c6,in0_8=>c7,K3=>w3,K2=>w2,
K1=>w1,sx0=>w6,out0=>w13);
m4:neimacs0 port map(in0_1=>d0,in0_2=>d1,in0_3=>d2,in0_4=>d3,
in0_5=>d4,in0_6=>d5,in0_7=>d6,in0_8=>d7,K3=>w3,K2=>w2,
K1=>w1,sx0=>w7,out0=>w12);
m5:shixusuccessful port map(b=>clk,S3=>w7,S2=>w6,
S1=>w5,S0=>w4);
m6:count16 port map(clk=>clk,D=>W1,C=>W2,B=>W3);
m7:men port map(in1=>w7,out1=>s3);
m8:men port map(in1=>w6,out1=>s2);
m9:men port map(in1=>w5,out1=>s1);
m10:men port map(in1=>w4,out1=>s0);
m11:andmen port map(in1=>w12,in2=>w13,in3=>w14,
in4=>w15,outp=>w16);
m12:djhlatch port map(D=>w16,ena=>ena,q1=>fujiout);
end Behavioral; |
