library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter3 is
port(clk,reset,en:in std_logic;
qa,qbut std_logic);
end counter3;
architecture behavior of counter3 is
signal count:std_logic_vector(1 downto 0);
begin
process(reset,clk)
begin
if reset='1'then
count(1 downto 0)<="00";
else
if(clk 'event and clk='1')then
if(en='1')then
if(count="10")then
count<="00";
else
count<=count+1;
end if;
end if;
end if;
end if;
end process;
qa<=count(0);
qb<=count(1);
end behavior;
上面这个是模3计数器的vhdl语言的程序，请问怎样把它改成模n计数器的程序？？
本人是初学的菜鸟，请各位高手指点一下，感激不尽阿~~！！！！
ut std_logic);
end counter3;
architecture behavior of counter3 is
signal count:std_logic_vector(1 downto 0);
begin
process(reset,clk)
begin
if reset='1'then
count(1 downto 0)<="00";
else
if(clk 'event and clk='1')then
if(en='1')then
if(count="10")then
count<="00";
else
count<=count+1;
end if;
end if;
end if;
end if;
end process;
qa<=count(0);
qb<=count(1);
end behavior;
上面这个是模3计数器的vhdl语言的程序，请问怎样把它改成模n计数器的程序？？
本人是初学的菜鸟，请各位高手指点一下，感激不尽阿~~！！！！