时序仿真与verilog编写语言不匹配，请问这是怎么回事 时序, verilog, 语言, 仿真, 编写

wenzi4402996

我用posedge 定义CLK、CLK4上升沿有效，c1，c2，c3，c4应该在CLK4的上升沿输出，但是时序图看到的却不是，请问这是什么原因？

module walsh4(clk,clk4,a1,b1,reset,c1,c2,c3,c4);
input clk;
input clk4;
input reset;
input[1:0]a1,b1;
output[3:0]c1,c2,c3,c4;
reg[3:0]c1,c2,c3,c4;
reg[1:0]x1,x2,x3,x4,a,b;
[email=always@(posedge]always@(posedge[/email] clk or negedge reset)
begin
if(~reset)//di dian ping you xiao
a<=0;
else
a<=a1;
case(a)
2'b00:begin
x1<=a;
end
2'b01:begin
x2<=a;
end
2'b10:begin
x3<=a;
end
2'b11:begin
x4<=a;
a<=2'b00;
end
default;
endcase
end
[email=always@(posedge]always@(posedge[/email] clk4 or negedge reset)
begin
if(~reset)//di dian ping you xiao
b<=0;
else
b<=b1;
case(b)
2'b00:begin
c1[3]<=x1[0]*b[0]+x1[1]*b[1];
c1[2]<=x2[0]*b[0]+x2[1]*b[1];
c1[1]<=x3[0]*b[0]+x3[1]*b[1];
c1[0]<=x4[0]*b[0]+x4[1]*b[1];
end
2'b01:begin
c2[3]<=x1[0]*b[0]+x1[1]*b[1];
c2[2]<=x2[0]*b[0]+x2[1]*b[1];
c2[1]<=x3[0]*b[0]+x3[1]*b[1];
c2[0]<=x4[0]*b[0]+x4[1]*b[1];
end
2'b10:begin
c3[3]<=x1[0]*b[0]+x1[1]*b[1];
c3[2]<=x2[0]*b[0]+x2[1]*b[1];
c3[1]<=x3[0]*b[0]+x3[1]*b[1];
c3[0]<=x4[0]*b[0]+x4[1]*b[1];
end
2'b11:begin
c4[3]<=x1[0]*b[0]+x1[1]*b[1];
c4[2]<=x2[0]*b[0]+x2[1]*b[1];
c4[1]<=x3[0]*b[0]+x3[1]*b[1];
c4[0]<=x4[0]*b[0]+x4[1]*b[1];
b<=2'b00;
end
default;
endcase
end
endmodule