哪位好心人看下Verilog的一段代码帮忙指导下

代码, Verilog, 指导, 好心人, 帮忙

哪位好心人看下Verilog的一段代码帮忙指导下加我QQ 991182024 谢谢
module TV_to_VGA (
OSC_27,
RESET,
VGA_BLANK,
VGA_SYNC,
VGA_CLOCK,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B,
TD_D,
TD_HS,
TD_VS
);
input    OSC_27;
input RESET;
output VGA_BLANK;
output VGA_SYNC;
output VGA_CLOCK;
output VGA_HS;
output VGA_VS;
output [7:0]VGA_R;
output [7:0]VGA_G;
output [7:0]VGA_B;
input [7:0]TD_D;
input TD_HS;
input TD_VS;

wire [7:0] Y;    //4:4:4 Y
wire [7:0] Cb;    //4:4:4 Cb
wire [7:0] Cr;    //4:4:4 Cr
wire mTD_HSx2;
wire [9:0]  R;
wire [9:0]  G;
wire [9:0]  B;
assign VGA_R={R[9:2]};
assign VGA_G={G[9:2]};
assign VGA_B={B[9:2]};
itu_r656_decoder U1
(
.CLOCK(OSC_27),  //system clock
.TD_D(TD_D[7:0]), //4:2:2 video data stream
  .TD_HS(TD_HS),  //Decoder_hs
.TD_VS(TD_VS),  //Decoder_vs
.Y(Y[7:0]),       //4:4:4 Y
.Cb(Cb[7:0]),    //4:4:4 Cb
.Cr(Cr[7:0]),    //4:4:4 Cr
.HSx2(mTD_HSx2),
.blank(VGA_BLANK)
);
YCbCr2RGB U2(
.Red(R[9:0]),
.Green(G[9:0]),
.Blue(B[9:0]),

.iY(~Y[7:0]),
//.iY((Y[7:0]>8'h90)? 8'hff: 8'h00),
//.iCb(Cb[7:0]),
//.iCr(Cr[7:0]),
.iCb(8'h80),
.iCr(8'h80),
.iRESET(!RESET),
.iCLK(OSC_27)
);
`include "VGA_Param.h"
reg  [10:0]L_COUNTER;//<<
reg  [10:0]RL_COUNTER;//<<
reg    [10:0]RL_COUNTER1;
wire  sync_reset=(RL_COUNTER>9)?1:0;//<<
//(RL_COUNTER==9)?1:0;//<<
//((RL_COUNTER==24)||(RL_COUNTER==25))?1:0;//<<
reg sync_en;//<<
reg [7:0]delay;//<<
reg  [9:0] H_Cont;
reg  [9:0] V_Cont;
reg oVGA_H_SYNC;
reg oVGA_V_SYNC;
reg Pre_HS;
reg Pre_VS;
reg mACT_HS;
reg mACT_VS;
[email=always@(posedge]always@(posedge[/email] OSC_27 or negedge sync_en)//<<
begin
if(!sync_en)//<<
begin
  Pre_HS  <= 0;
  mACT_HS  <= 0;
  H_Cont  <= 0;
  oVGA_H_SYNC <= 0;
end
else
begin
  Pre_HS <= mTD_HSx2;
  if({Pre_HS,mTD_HSx2}==2'b10)
  mACT_HS <= 1;
  if(mACT_HS)
  begin
// H_Sync Counter
if( H_Cont < 858 )
H_Cont <= H_Cont+1;
else
begin
H_Cont <= 0;
mACT_HS <= 0;
end
// H_Sync Generator
if( H_Cont < H_SYNC_CYC )
oVGA_H_SYNC <= 0;
else
oVGA_H_SYNC <= 1;
  end
  else
  begin
oVGA_H_SYNC <= 0;
H_Cont  <= 0;
  end
end
end
[email=always@(posedge]always@(posedge[/email] OSC_27 or negedge sync_en)//<<
begin
if(!sync_en)//<<
begin
  Pre_VS  <= 1;
  mACT_VS  <= 0;
  V_Cont  <= 0;
  oVGA_V_SYNC <= 0;
end
else
begin
  Pre_VS <= TD_VS;
  if({Pre_VS,TD_VS}==2'b01)
  mACT_VS <= 1;
  if( (H_Cont==1) && mACT_VS)
  begin
// V_Sync Counter
if( V_Cont < 624 )
V_Cont <= V_Cont+1;
else
V_Cont <= 0;
// V_Sync Generator
if( V_Cont < V_SYNC_CYC )
oVGA_V_SYNC <= 0;
else
oVGA_V_SYNC <= 1;
  end
end
end
assign VGA_HS  = oVGA_H_SYNC;
assign VGA_VS  = oVGA_V_SYNC;
assign VGA_SYNC = 1'b0; //sync始终有效
assign VGA_CLOCK = OSC_27; //象素时钟
//>>lock detector
always @(posedge TD_HS)
begin
if (TD_VS) L_COUNTER=0; //遇到场同步，行计数清零
else L_COUNTER=L_COUNTER+1;//否则行计数+1
end
always @(posedge TD_VS)    //TD_VS上深沿行计数保存到RL_COUNTER
begin
  RL_COUNTER=L_COUNTER; //1714
end
[email=always@(negedge]always@(negedge[/email] sync_reset or posedge TD_VS)
begin
if (!sync_reset)
  delay=0;
else if (delay < 100)
  delay=delay+1;
end
[email=always@(negedge]always@(negedge[/email] sync_reset or negedge TD_VS) begin
if (!sync_reset)
  sync_en=0;
else if (delay < 50)
sync_en=0;
else
sync_en=1;
end
//<<
endmodule

收藏分享评分

回复引用

订阅 TOP