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[求助]显示器扫描程序

[求助]显示器扫描程序

高手们,帮我看看这个程序好吗?我做的是一个显示器的扫描程序,大小为525×800,但有效行为480,每行有效点为640,其余为消隐时间间隔。我现在要把colo中的8个8位的数据分别送给(180,250)到(187,258)之间的8×8的矩阵点,并且让数据位为1的点显示为亮点,即grbp=110,我用了一个地址计数参数和一个循环移动参数来控制数据的输出,并且把输出数据和循环移动参数相与后判断哪位数据为1,但现在地址计数参数不能自动加一,即不能更新,所以始终是初始值,能帮我看看吗?谢谢了,我搞了几天了,还是想不通,附件上传不了,是一个8个8位的数据。谢谢了 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity color10 is port(clk:in std_logic; r,g,b,hs,vsut std_logic); end color10; architecture behav of color10 is signal hs1,vs1,fclk,cclk:std_logic; signal fs:integer range 0 to 1; signal cc:std_logic_vector(9 downto 0 ); --行扫描计数 signal ll:std_logic_vector(9 downto 0 ); --场扫描计数 signal grbp:std_logic_vector(3 downto 1 ); signal grb:std_logic_vector(3 downto 1 ); signal SCAN_CODE : STD_LOGIC_VECTOR (7 downto 0); signal SCAN_LINE : STD_LOGIC_VECTOR(7 downto 0);--循环移动 signal SCAN_COUNT : STD_LOGIC_VECTOR(2 downto 0);--地址计数 signal iFONT_CODE ,iscan_code: STD_LOGIC_VECTOR(7 downto 0); signal iSCAN_ADDR : STD_LOGIC_VECTOR(2 downto 0); component colo PORT ( address: IN STD_LOGIC_VECTOR (2 DOWNTO 0); q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); end component; begin grb(2)<=grbp(2) and hs1 and vs1; grb(3)<=grbp(3) and hs1 and vs1; grb(1)<=grbp(1) and hs1 and vs1; process(clk) begin if clk'event and clk='1' then --50MHz 2分频 if fs=1 then fs<=0;fclk<='0'; else fs<=fs+1;fclk<='1'; end if; end if; end process; process(fclk) begin if fclk'event and fclk='1' then if cc=799 then cc<="0000000000"; elsif cc=249 then cc<=cc+1; SCAN_LINE <= "10000000"; elsif cc<258 and cc>249 then cc<=cc+1; SCAN_LINE <= SCAN_LINE(0) & SCAN_LINE(7 downto 1) ; -- rotate right else cc<=cc+1; scan_line<="00000000"; end if; end if; end process; cclk<=cc(9); process(cclk) begin if cclk'event and cclk='0' then if ll=481 then ll<="0000000000"; elsif ll=179 then ll<=ll+1; scan_count <= "000"; elsif ll<188 and ll>179 then ll<=ll+1; scan_count <= scan_count + 1; else ll<=ll+1; scan_count <= "111"; end if; end if; end process; process(cc,ll) begin if cc>639 then hs1<='0'; --行同步 else hs1<='1'; end if; if ll>479 then vs1<='0'; --场同步 else vs1<='1'; end if; end process; iSCAN_ADDR <= SCAN_COUNT; SCAN_CODE <= iFONT_CODE and scan_line; U1: colo Port Map ( address => iSCAN_ADDR, q => iFONT_CODE ); process(scan_code) begin for i in 0 to 7 loop if scan_code(i)='1' then grbp<="110"; else grbp<="000"; end if; end loop; end process; hs<=hs1; vs<=vs1; r<=grb(2); g<=grb(3); b<=grb(1); end behav;
不懂VHDL,不过帮顶
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