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- UID
- 122005
- 性别
- 男
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添加了需要的模块,然后generate的时候选择了HDL.Generate system module logic in Verilog选项后,出现下面的提示
Altera SOPC Builder Version 5.00 Build 148
Copyright (c) 1999-2005 Altera Corporation. All rights reserved.
# 2005.09.16 16:40:16 (*) mk_custom_sdk starting
# 2005.09.16 16:40:16 (*) Reading project C:/wave/fpga/tsunami_tutorial/Example.ptf.
# 2005.09.16 16:40:16 (*) Finding all CPUs
# 2005.09.16 16:40:16 (*) Finding all peripherals
# 2005.09.16 16:40:16 (*) Finding software components
# 2005.09.16 16:40:16 (*) mk_custom_sdk finishing
# 2005.09.16 16:40:16 (*) Starting generation for system: Example.
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..
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# 2005.09.16 16:40:18 (*) Running Generator Program for plx9656_avalon_bridge_0
---------------------
WIZARD PARAMS:
---------------------
"do_read_ahead_a" "0"
"do_read_ahead_b" "0"
"maximum_read_latency" "127"
"do_read_ahead_c" "0"
"do_latent_read_a" "1"
"do_latent_read_b" "1"
"do_latent_read_c" "1"
"use_port_a" "1"
"use_port_b" "0"
"enable_interrupt_controller" "0"
"use_port_c" "1"
"do_constant_address_a" "0"
"do_constant_address_b" "1"
"block_minor_rev" "2"
"copy_files" "*.vhd *.tdf *.inc"
"do_constant_address_c" "0"
"block_major_rev" "0"
"fpga_id_register" "0xabcdefab"
"vhd_top" "plx9656_avalon_bridge"
Copying *.vhd ...
'cp' 不是内部或外部命令，也不是可运行的程序
或批处理文件。
Copying *.tdf ...
'cp' 不是内部或外部命令，也不是可运行的程序
或批处理文件。
Copying *.inc ...
'cp' 不是内部或外部命令，也不是可运行的程序
或批处理文件。
top = plx9656_avalon_bridge
'mv' 不是内部或外部命令，也不是可运行的程序
或批处理文件。
Can not open C:/wave/fpga/tsunami_tutorial/plx9656_avalon_bridge_0.vhd No such file or directory
Error: Generator program
for module 'plx9656_avalon_bridge_0' did NOT run successfully.
generator cmd was 'c:/altera/quartus50//bin/perl561/bin/perl -Ic:/altera/quartus50/sopc_builder/bin -Ic:/altera/quartus50/sopc_builder/bin/europa -Ic:/altera/quartus50/sopc_builder/bin/perl_lib -I. -IC:/wave/fpga/sopc_components/sbs_plx9656_avalon_bridge -Id:/altera/kits/nios2/components/altera_nios_dev_board_stratix_1s10_es -Id:/altera/kits/nios2/components/altera_nios_dev_board_stratix_2s60_es -ID:/altera/MegaCore/ddr_ddr2_sdram-v3.1.0/lib/sopc_builder/ddr2_sdram_component -Id:/altera/kits/nios2/components/altera_nios_custom_instr_endian_converter -IC:/wave/fpga/sopc_components/sbs_avalon_camera_emulator -Ic:/altera/nioskits/components/altera_nios -Id:/altera/kits/nios2/components/amd_avalon_am29lv128m_flash -Ic:/altera/nioskits/components/altera_nios_dev_board_flash -Id:/altera/kits/nios2/components/amd_avalon_am29lv065d_flash -Id:/altera/kits/nios2/components/altera_nios_dev_kit_stratix
_edition_sram -Ic:/altera/quartus50/sopc_builder/components/altera_sopc_builder -Id:/altera/kits/nios2/components/altera_nios_dev_board_stratix_1s40 -Id:/altera/kits/nios2/components/altera_nios2 -Ic:/altera/quartus50/sopc_builder/components/altera_avalon_clock_adapter -IC:/wave/fpga/sopc_components/sbs_avalon_interrupt_controller -Id:/altera/kits/nios2/components/altera_avalon_spi -IC:/wave/fpga/sopc_components/sbs_avalon_capture_control -IC:/wave/fpga/sopc_components/sbs_avalon_camera_control -IC:/wave/fpga/sopc_components/sbs_generator -Id:/altera/kits/nios2/components/altera_avalon_cfi_flash -IC:/wave/fpga/sopc_components/sbs_avalon_dma_demand_mode_fifo -Ic:/altera/quartus50/sopc_builder/components/altera_avalon_dma -Ic:/altera/quartus50/sopc_builder/components/altera_ahb_avalon_bridge -Ic:/altera/quartus50/sopc_builder/components/altera_avalon_avalon_ahb_bridge -Ic:/altera/quartus50/sopc_builder/components/altera_avalon_tri_state_bridge -Id:/altera/kits/nios2/components/altera_nios_eval_board_cyclone_1c1
2 -Id:/altera/kits/nios2/components/altera_avalon_lan91c111 -IC:/wave/fpga/sopc_components/sbs_avalon_pixel_reorder -Id:/altera/kits/nios2/components/altera_avalon_lcd_16207 -Id:/altera/kits/nios2/components/altera_nios_dev_kit_stratix_edition_sram2 -Ic:/altera/quartus50/sopc_builder/components/altera_avalon_burst_adapter -Id:/altera/kits/nios2/components/altera_nios_multiply -IC:/wave/fpga/sopc_components/sbs_avalon_io_cameralink -Id:/altera/kits/nios2/components/altera_nios_dev_board_cyclone_1c20 -Ic:/altera/quartus50/sopc_builder/components/altera_avalon_user_defined_interface -Id:/altera/kits/nios2/components/altera_avalon_cs8900 -Id:/altera/kits/nios2/components/altera_plugs_library -Id:/altera/kits/nios2/components/altera_nios_dev_board_stratix_1s10 -IC:/wave/fpga/sopc_components/sbs_avalon_io_encoder_trigger -Id:/altera/kits/nios2/components/altera_avalon_jtag_uart -Id:/altera/kits/nios2/components/altera_avalon_asmi -Ic:/altera/quartus50/sopc_builder/components/altera_avalon_onchip_memory -IC:/wave/fp
ga/sopc_components/sbs_avalon_lval_generator -Ic:/altera/nioskits/components/altera_nios_dev_board_sram32 -Id:/altera/kits/nios2/components/altera_dsp_dev_board_stratix_2s60_es -Id:/altera/kits/nios2/components/altera_avalon_onchip_memory2 -Ic:/altera/nioskits/components/altera_nios_custom_instr_divide -Id:/altera/kits/nios2/components/altera_avalon_timer -Id:/altera/kits/nios2/components/altera_avalon_new_sdram_controller -Id:/altera/kits/nios2/components/altera_nios_custom_instr_bitswap -ID:/altera/MegaCore/ddr_ddr2_sdram-v3.1.0/lib/sopc_builder/ddr_sdram_component -Id:/altera/kits/nios2/components/altera_avalon_performance_counter -Id:/altera/kits/nios2/components/altera_avalon_epcs_flash_controller -IC:/wave/fpga/sopc_components/sbs_avalon_lval_window -Id:/altera/kits/nios2/components/altera_avalon_sysid -Id:/altera/kits/nios2/components/altera_avalon_mutex -Id:/altera/kits/nios2/components/altera_avalon_uart -Id:/altera/kits/nios2/components/altera_nios_custom_instruction -IC:/wave/fpga/sopc_components/s
bs_plx9656_avalon_bridge -Id:/altera/kits/nios2/components/altera_user_board_setup -Ic:/altera/nioskits/components/altera_avalon_sdram_controller -Id:/altera/kits/nios2/components/altera_avalon_pio C:/wave/fpga/sopc_components/sbs_plx9656_avalon_bridge/local_generator.pl --system_name=Example --target_module_name=plx9656_avalon_bridge_0 --system_directory=C:/wave/fpga/tsunami_tutorial --sopc_directory=c:/altera/quartus50/sopc_builder --sopc_lib_path=C:/wave/fpga/tsunami_tutorial+C:/wave/fpga/sopc_components+D:/altera/MegaCore/ddr_ddr2_sdram-v3.1.0/lib/sopc_builder+d:/altera/kits/nios2/components+c:/altera/nioskits/components+c:/altera/quartus50/sopc_builder/components --generate=1 --verbose=0 --software_only=0 --module_lib_dir=C:/wave/fpga/sopc_components/sbs_plx9656_avalon_bridge --sopc_quartus_dir=c:/altera/quartus50/ --projectname=TsunamiDemo.quartus '
Error in processing. System NOT successfully generated.
不知道是为什么,这只是一个范例,设计本身应该没什么问题啊,但是需要.v的或者.vhd的文件,所以必须要选这个选项,请高手指点一下迷津
另外就是别的设计出来的niosII.v的文件是不是就是niosIIcpu的硬件描述语言设计,难道altera公司不进行加密? |
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