| LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shift_circle2 IS
PORT(
clk :IN STD_LOGIC;
ena :IN STD_LOGIC;
reset:IN STD_LOGIC;
q :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END shift_circle2;
ARCHITECTURE behavier OF shift_circle2 IS
CONSTANT A: STD_LOGIC_VECTOR(2 DOWNTO 0):="001";
CONSTANT B: STD_LOGIC_VECTOR(2 DOWNTO 0):="010";
CONSTANT C: STD_LOGIC_VECTOR(2 DOWNTO 0):="100";
SIGNAL present_state:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL next_state:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(reset,clk)
BEGIN
IF(reset='1') THEN
present_state<=A;
ELSIF(clk'EVENT AND clk='1') THEN
present_state<=next_state;
END IF;
END PROCESS;
PROCESS(clk)
BEGIN
CASE present_state IS
WHEN A =>
IF ena='1' THEN
next_state<=B;
END IF;
WHEN B =>
IF ena='1' THEN
next_state<=C;
END IF;
WHEN C =>
IF ena='1' THEN
next_state<=A;
END IF;
WHEN OTHERS =>
next_state<=A;
END CASE;
END PROCESS;
q<=present_state;
END behavier;
大家看仿真后波形，请问present_state为什么会是这样？ |
