用verilog写的电子时钟的程序 电子, initial, 程序

wxg1988

用verilog写的电子时钟的程序
哈哈，我干了俩天俩夜，大家参考．
module wyptime(cp,con, oth,otm,ots,ch,cm    );
   input        con,cp,ch,cm;
   output[5:0] oth,otm,ots;
   reg[5:0]     oth,otm,ots,oth1,otm1;
   reg          cp1,c;
   /*仿真赋初值*/
   initial
    begin
     oth=0;otm=0;ots=0;oth1=0;otm1=0;cp1=0;c=0;
    end
/*分频功能*/
[email=always@(posedge]always@(posedge[/email] cp)
   begin
    c=c+1;if(c==1)cp1=~cp1;
   end
  
/*完成计时功能*/
always @(posedge cp1 or negedge con     )
begin
   
if(~con) begin oth=oth1;otm=otm1;end //若控制端有效，完成校时功能
    else begin       ots=ots+1;
   if(ots==60)     begin ots=0;otm =otm +1; end
   if(otm==60)     begin otm=0;oth =oth +1;end
   if(oth==12)     begin oth=0; end
   
end
end
/*对小时和分进行校准*/
[email=always@(posedge]always@(posedge[/email] ch )
begin
   oth1=oth1+1;if(oth1==12)   oth1=0;
end
[email=always@(posedge]always@(posedge[/email] cm )
begin
   otm1=otm1+1; if(otm1==60) otm1=0;
end

endmodule