帮忙看下这个记数器程序错在哪里了.
library ieee;
use ieee.std_logic_1164.all;
entity counter is
port
(clock:in std_logic;
reset:in std_logic;
hold:in std_logic;
countnum:buffer integer range 0 to 59
);
end;
architecture behavior of counter is
begin
process(reset,clock)
begin
if reset='1' then
countnum<=0;
else
if rising_edge(clock)then
if hold='1' then
countnum<=countnum;
else
if countnum=59 then
countnum<=0;
else
countnum<=countnum+1;
end if;
end if;
end if;
end process;
end;
谢谢各位了!
