一个问题 carry

wz1981

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clkgen is
port(sysres,en1,clk:in std_ulogic;
     cntclk,keyclkut std_ulogic);
end clkgen;

architecture rt1 of clkgen is
component cnt10
port(reset,en,clk:in std_ulogic;
     carryut std_ulogic;
     qut std_ulogic_vector(3 downto 0));
end component;
  
component cnt4
port(reset,en,clk:in std_ulogic;
           carryut std_ulogic;
            qut std_ulogic_vector(1 downto 0));
end component;
signal cntclk_s:std_ulogic;
begin
u0:cnt10 port map(sysres,en1,clk,cntclk_s);
u1:cnt4  port map(sysres,cntclk_s,clk,keyclk);
cntclk<=cntclk_s;
end rt1;
这段代码错误说error:line 13: unsupported feature error:enumeration type definition not supported in port declaration of the component instantiation statement.
我看例化的结构好象没什么问题嘛!请高手指点下
谢谢