| 我已经郁闷了很久了,在Xilinx ISE 下利用Modelism进行时序仿真的时候出现这种错误,请各位帮我分析一下,什么原因啊?谢谢
# Region: /my_test/UUT
# ** Error: (vsim-3063) my_test.timesim_tfw(108): Port 'LA' not found in the connected module (31st connection).
# Region: /my_test/UUT
# ** Warning: (vsim-3722) my_test.timesim_tfw(108): [TFMPC] - Missing connection for port '\LA[2]\'.
# ** Warning: (vsim-3722) my_test.timesim_tfw(108): [TFMPC] - Missing connection for port '\LA[3]\'.
# ** Warning: (vsim-3722) my_test.timesim_tfw(108): [TFMPC] - Missing connection for port '\LA[9]\'.
# ** Warning: (vsim-3722) my_test.timesim_tfw(108): [TFMPC] - Missing connection for port '\LA[10]\'.
# ** Warning: (vsim-3722) my_test.timesim_tfw(108): [TFMPC] - Missing connection for port '\LA[8]\'.
# Loading d:\modeltech_5.8c\xilinx_libs\simprims_ver.ffsrce
# Error loading design
解释:
LA[10:2}是我定义的一组地址输入信号 | 
