一个简单的VHDL程序：
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY clear IS
PORT(COE_in:IN std_logic;
clear:OUT std_logic);
END clear;
ARCHITECTURE rtl OF clear IS
signal temp:std_logic;
BEGIN
PROCESS(COE_in)
BEGIN
IF COE_in='1'and COE_in'EVENT THEN
temp<='1';
else
temp<='0';
END IF;
clear<=temp;
END PROCESS;
END rtl;
check 没错
生成宏的时候会出现：
Create chip...
Error: Illegal assignment to 'temp'. It depends on a non-edge
in routine clear line 25 in file 'an/my project/test/mytest/DPMCOMP.TMP/files' (HDL-110)
怎么回事 ？高手告诉一下好不。
[此贴子已经被作者于2005-12-1 12:17:19编辑过]
[此贴子已经被作者于2005-12-1 15:17:23编辑过] | 
