Library ieee;
use iee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg is
port(d:in std_logic;
clk:in std_logic;
qut std_logic);
end reg;
architecture behavior of reg is
component dff
port(d:in std_logic;
clk:in std_logic;
qut std_logic);
end component;
signal wd:std_logic;
signal wq:std_logic;
signal wc:std_logic;
begin
u1:dff port map(wd,wq,wc);
……
End behavior;