請問如何正確的使用rol移位運算子 rol, 移位

johny862

Dear All:

我的VHDL程式碼如下

============================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

entity differ is
    Port (  clk : in std_logic;
           q : out std_logic_vector(3 downto 0)
);
end differ;

architecture Behavioral of differ is
signal sck:unsigned(3 downto 0):="0110";
signal sck1:unsigned(3 downto 0):="0000";
begin
process(clk)
begin
if (clk'event and clk='1') then
sck1<=sck rol 1 ;
end if;
end process;
end Behavioral;

=======================================


在合成的過程中 卻有問題
1.我有use ieee.numeric_std.all;
2.當我去看numeric_std.vhd的根據它的如下

------------------------------------------------------------------------------
  --   Note : Function S.13 is not compatible with
VHDL 1076-1987. Comment
  -- out the function (declaration and body) for VHDL
1076-1987 compatibility.

------------------------------------------------------------------------------
  -- Id: S.13
  function "rol" (ARG: UNSIGNED; COUNT: INTEGER)
  return UNSIGNED;
  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
  -- Result: ROTATE_LEFT(ARG, COUNT)


  運算元是要用unsigned 的形式而我也用了
  但是合成卻出現 如下的錯誤訊息

  rol can not have such operands in this context.

麻煩幫我看一下哪裡有錯誤 thanks