implement错误 register, 信号

gxiaob

我在chipscope的cdc文件中的net selection中加入一些信号后，在implement时出现如下错误，/////////////////////////////////////////////////////////////////////
genvar addr_i;
generate
for (addr_i = 0; addr_i < ROW_WIDTH; addr_i = addr_i + 1) begin: gen_addr
(* IOB = "FORCE" *) FDCPE u_ff_addr
(
.Q (ddr_addr[addr_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (addr_mux[addr_i]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
endgenerate
Pack:1560 - The register "u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_ctl_io/gen_ba[0].u_ff_ba" has the property IOB=FORCE, but was not packed into the OLOGIC component. The output signal for register symbol u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_ctl_io/gen_ba[0].u_ff_ba requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.
///////////////////////////////////////////////////////////////////////////////////////////////////
genvar rden_i;
generate
for (rden_i = 0; rden_i < DQS_WIDTH; rden_i = rden_i + 1) begin: gen_rden
SRLC32E u_rden_srl
(
.Q (rden_srl_out[rden_i]),
.Q31 (),
.A ({rden_dly_r[(rden_i*5)+4],
rden_dly_r[(rden_i*5)+3],
rden_dly_r[(rden_i*5)+2],
rden_dly_r[(rden_i*5)+1],
rden_dly_r[(rden_i*5)]}),
.CE (1'b1),
.CLK (clk),
.D (ctrl_rden_r)
);
"u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_rden[4].u_rden_srl"has no output pin connections
请问上述错误是什么意思，如何修改，谢谢！