我调用了一个DCM，输入输出直接MAP出来。为什么仿真结果倍频出不来，请高手帮帮忙！！！！
难道DCM不能这么用？
输入24MHZ，想出来48MHZ。而且 下图是CLKIN_IN在下降沿时才出来的，上升沿只有LOCK有输出。
上升沿
entity yl is
PORT(
CLKIN_IN : IN std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
CLK2X_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
end yl;
architecture Behavioral of yl is
signal a: std_logic;
COMPONENT dcm1
 ORT(
CLKIN_IN : IN std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
CLK2X_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
begin
Inst_dcm1: dcm1 PORT MAP(
CLKIN_IN =>CLKIN_IN ,
CLKIN_IBUFG_OUT => CLKIN_IBUFG_OUT ,
CLK0_OUT => CLK0_OUT,
CLK2X_OUT =>a ,
LOCKED_OUT => LOCKED_OUT
);
CLK2X_OUT<=a;
end Behavioral;
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