module bit_compare
(
ck,
reset,
a,
b,
false,
counter
);
input ck;
input reset;
input a;
input b;
output false;
output[3:0] counter;
//----------------------------------------------------
reg false;
reg[3:0] counter;
always @ ( posedge ck or negedge reset )
begin
if( ~reset )//reset==0
begin
false <=0;
counter <=0;
end
else
begin
if(a!=b)
begin
counter <= counter +1;
end
if(counter>7)
begin
false <=1;
end
end
end
endmodule
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