如何仿真IP核（建立modelsim仿真库完整解析）:资料
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- 131591
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- 男
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- UID
- 131591
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- 男
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我是在ISE中直接调用Modelsim进行仿真的，IP核已经例化。但在仿真中还是报错
给解释一下吧
Loading work.testfifo_v
# Loading work.top1
# ** Error: (vsim-3033) top1.v(54): Instantiation of 'myfifo' failed. The design unit was not found.
# Region: /testfifo_v/uut
# Searched libraries:
# d:\Modeltech_xe\win32xoem/../xilinx/verilog/xilinxcorelib_ver
# d:\Modeltech_xe\win32xoem/../xilinx/verilog/unisims_ver
# work
# Loading work.glbl
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./testfifo_v.fdo PAUSED at line 8 |
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- 128157
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- 153054
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____ ____
/ /\/ /
/___/ \ / VENDOR : Xilinx Inc.
\ \ \/ VERSION : 9.1.03i (J.33)
\ \ APPLICATION : compxlib
/ / CONTENTS : Compilation Log
/___/ /\ FILENAME : compxlib.log
\ \ / \ CREATED ON : THU 26 APR 20:32:27 2007
\___\/\___\ XILINX = 'C:\Xilinx91i'
Library Source => 'C:\Xilinx91i' Compilation Mode = FAST
Scheduling library compilation for VIRTEX-II Signature:-
------------------------------------------------------------------------------
compxlib -s mti_se
-arch virtex2
-lib unisim
-lib simprim
-lib xilinxcorelib
-l vhdl
-dir C:\Xilinx91i
-log compxlib.log
-w
------------------------------------------------------------------------------
ERROR:CAEInterfaces - COMPXLIB[env]: unable to automatically find simulator (mti_se) executables. 就是这个，我按照文档操作的，附A部分，在ise中调用modelsim，在ise中编译库时出现错误，怎么办？开了个新贴。
[此贴子已经被作者于2007-4-26 20:48:17编辑过] |
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| 正需要这方面的东西呢 1# pengyoubieku |
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1# pengyoubieku
感谢呀！！！！！！！！！ |
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